EPM9320RI208-20N vs EPM9560RI208-15N Vergleich

Detaillierter Direktvergleich von EPM9320RI208-20N von Altera und EPM9560RI208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320RI208-20N EPM9560RI208-15N
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $0,00 $19,45
Device Family MAX 9000 (EPM9320) MAX 9000
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Macrocells 320 —
Flip-Flops 484 —
Propagation Delay (tPD) 20 ns 11.4 ns (15 ns speed grade)
Supply Voltage (VCC) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5 V configurable —
Gehäuse 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (Ruggedized Quad Flat Pack)
Package Lead Pitch 0.500 mm —
Number of Terminals 208 —
Betriebstemperaturbereich -40C to +85C (Industrial) —
In-System Programmability Yes, 5.0 V ISP via JTAG —
JTAG Interface IEEE Std. 1149.1 compliant —
Configuration Memory EEPROM (non-volatile) CMOS EEPROM, in-system programmable
Dedicated Input Pins 4 (low-skew global distribution) —
Minimum DC Input on I/O Pins -0.5 V —
Minimum DC Input on Dedicated Inputs -0.3 V —
Input Undershoot/ Overshoot -2.0 V / 7.0 V for <20 ns (no-load) —
Montageart Surface Mount —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Manufacturer — Altera (Intel Programmable Solutions Group)
Device Type — EPLD (Erasable Programmable Logic Device)
Architecture — Multiple Array MatriX (MAX), 3rd generation
Total Pins — 356 (per third-party catalog; see _validation_note)
Package Pin Count — 208
Terminal Form — Gull Wing
Package Code — HFQFP
User I/Os — 216 (per DigiChip specification; see _validation_note)
Maximum Internal Frequency — 145 MHz
Speed Grade — -15
Versorgungsspannung — 5.0 V
Betriebstemperatur — 0C to 70C (Commercial)
Temperature Grade — Industrial (per Vyrian/Partstack listings)
Logic Family — CMOS
Programming Interface — IEEE 1149.1 JTAG, 5.0-V in-system

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern