EPM9560ARC208-10N vs EPM9560ARI208-10N Vergleich
Detaillierter Direktvergleich von EPM9560ARC208-10N von Altera und EPM9560ARI208-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM9560ARC208-10N | EPM9560ARI208-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $22,10 |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Internal Counter Frequency | 144.9 MHz | — |
| Versorgungsspannung | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Gehäuse | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Plastic) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 C to +70 C (commercial) | 0 C to 70 C (Commercial) |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | — |
| Logic Array Blocks (LABs) | 20 | 35 |
| Speed Grade | -10 | — |
| RoHS-Status | Compliant (N suffix) | — |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 212 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD1) | — | 10 ns |
| Clock-to-Output (tCO) | — | 4.5 ns |
| Setup Time (tSU) | — | 3.0 ns |
| Maximum Counter Frequency (fCNT) | — | 144.9 MHz |
| Logic Family | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) - In-System Programmable |