EPM9560GC280-20 vs EPM9320GC280-15 Vergleich
Detaillierter Direktvergleich von EPM9560GC280-20 von Altera und EPM9320GC280-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteSpezifikationsvergleich
| Parameter | EPM9560GC280-20 | EPM9320GC280-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $360,00 | $92,50 |
| Family | MAX 9000 | MAX 9000 (EPM9320) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Usable Gates | 12,000 | 6,000 |
| Macrocells | 560 | 320 |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | — |
| Gehäuse | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Betriebstemperatur | [DATA_NEEDED: commercial/industrial/military grade] | 0 C to +70 C (commercial) |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| Montageart | Through-Hole (CPGA socket) | Through-hole (PGA socket) |
| RoHS-Status | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | ROHS3 compliant (per fpgalink listing) |
| Architecture | — | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Logic Array Blocks (LABs) | — | 20 (16 macrocells per LAB) |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Maximum User I/O Pins | — | 164 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| I/O Voltage Levels | — | 3.3 V or 5 V (configurable) |
| Programmability | — | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| MSL-Level | — | 3 (168 hours) |
| Technology Node | — | CMOS EEPROM, third-generation MAX |