EPM9560R1208-20 vs EPM9560RC-15 Vergleich
Detaillierter Direktvergleich von EPM9560R1208-20 von Altera und EPM9560RC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9560R1208-20 | EPM9560RC-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,40 | $30,10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks | 52 (typical for 560 macrocells) | — |
| Maximum User I/O | 212 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (5.0 V ISP via JTAG) |
| Betriebstemperatur | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Gehäuse | R-1208 (BGA-style fine-pitch) | 240-pin RQFP (32x32 mm) |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | Multiple Array MatriX (MAX) - third generation |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| RoHS-Status | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 16 (40 macrocells each) |
| Maximum User I/O Pins | — | 191 |
| Pin-to-Pin Delay (tPD1) | — | 15 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |