EPM9560RC208-10 vs EPM9560RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9560RC208-10 von Intel und EPM9560RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC208-10 | EPM9560RC208-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,40 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 (208-pin package variant) | — |
| Usable Gates | 12,000 | 12,000 gates |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: internal toggle frequency in MHz] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standards Supported | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) | — |
| Configuration Memory | EEPROM (in-system programmable via JTAG) | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Gehäuse | 208-pin RQFP (Plastic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Lead-Free | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] | — |
| RoHS-Status | [DATA_NEEDED: not stated in retrieved distributor listings] | [DATA_NEEDED: RoHS status] |
| Programmability | JTAG (IEEE 1149.1) in-system programming | — |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Versorgungsspannung | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |