EPM9560RC208-17 vs EPM9560RC208-12 Vergleich
Detaillierter Direktvergleich von EPM9560RC208-17 von Altera und EPM9560RC208-12 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC208-17 | EPM9560RC208-12 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $54,75 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (EPLD, in-system programmable) | — |
| Usable Gates | 12,000 | 12000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 17 ns | — |
| Maximum Counter Frequency | 117.6 MHz | — |
| User I/O Pins | 212 | — |
| Supply Voltage (VCC) | 5 V | — |
| Gehäuse | 208-pin RQFP (RC208) | 208-pin RQFP (S-PQFP-G208) |
| Programming Technology | EEPROM (in-system programmable) | — |
| Program/Erase Cycles | 100 minimum | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Architecture | Third-generation MAX (AND-OR PLA) | — |
| Montageart | Surface Mount | Surface Mount |
| Device Type | — | EEPROM-based CPLD |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Propagation Delay (tPD) | — | 12 ns |
| Maximale Taktfrequenz | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.50 mm |
| Betriebstemperatur | — | 0C to +70C (commercial) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks | — | 20 |
| Speed Grade | — | -12 (12 ns) |
| RoHS-Status | — | [DATA_NEEDED: RoHS status] |