EPM9560RC208-19 vs EPM9560RC208-17 Vergleich
Detaillierter Direktvergleich von EPM9560RC208-19 von Altera und EPM9560RC208-17 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC208-19 | EPM9560RC208-17 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $54,75 |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (EPLD, in-system programmable) |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| Flip-Flops | 772 | — |
| User I/O Pins | 149 | 212 |
| Propagation Delay (tPD) | 19 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V / 5 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Technology | CMOS EEPROM | — |
| Gehäuse | RQFP-208 (208-pin PQFP) | 208-pin RQFP (RC208) |
| JEDEC Package Code | S-PQFP-G208 | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Family | — | MAX 9000 |
| Macro Cells | — | 560 |
| Pin-to-Pin Delay (tPD) | — | 17 ns |
| Maximum Counter Frequency | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| Program/Erase Cycles | — | 100 minimum |
| JTAG (IEEE 1149.1) Support | — | Yes |
| Architecture | — | Third-generation MAX (AND-OR PLA) |