EPM9560WC208-15 vs EPM9560RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9560WC208-15 von Altera und EPM9560RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560WC208-15 | EPM9560RC208-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $105,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Technology | CMOS | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Flip-Flops | 772 | — |
| User I/O Pins (max) | 149 | — |
| Maximale Taktfrequenz | 117.6 MHz | — |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | -15 (15 ns pin-to-pin) |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Gehäuse | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| RoHS-Status | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 12,000 gates |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Versorgungsspannung | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |