LCMXO2-640HC-4TG100C vs LCMXO2-1200HC-4TG100C Vergleich
Detaillierter Direktvergleich von LCMXO2-640HC-4TG100C von Lattice Semiconductor und LCMXO2-1200HC-4TG100C von Lattice Semiconductor. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Lattice Semiconductor
LCMXO2-640HC-4TG100C - 640 LUT MachXO2 FPGA, 100-LQFP | Lattice
LCMXO2-640HC-4TG100C ✓ AktivLattice Semiconductor
LCMXO2-1200HC-4TG100C - 1280-LUT 3.3V FPGA | Lattice
LCMXO2-1200HC-4TG100C ✓ AktivSpezifikationsvergleich
| Parameter | LCMXO2-640HC-4TG100C | LCMXO2-1200HC-4TG100C |
|---|---|---|
| Marke | Lattice Semiconductor | Lattice Semiconductor |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,10 | $13,45 |
| Family | MachXO2 | — |
| Logic Elements / LUTs | 640 LUTs (4-input) | — |
| Number of PLDs (Logic Blocks) | 80 | — |
| Distributed RAM | Up to 18.4 kbits (640 LUTs x 32 bits) | Up to 54 kbits |
| Embedded Block RAM (EBR) | 18,432 bits (2 x 9 kbit blocks) | — |
| Number of User I/Os | 78 | — |
| Number of Macrocells | 320 | — |
| Maximum Operating Frequency | 136.6 MHz | — |
| Programmable Type | In System Programmable (Flash + SRAM) | — |
| Core Voltage (Vcc) | 3.3 V (typical HC grade) | — |
| I/O Voltage (Vccio) | 2.5 V / 3.3 V | — |
| I/O Standards Supported | LVCMOS 1.2-3.3 V, LVDS, LVPECL, programmable differential | — |
| Standby Power | As low as 22 µW | As low as 22 uW |
| Process Technology | 65 nm low-power CMOS | — |
| Gehäuse | 100-pin TQFP (TG100), 14 x 14 mm | TG100, 100-pin TQFP, 14 x 14 mm |
| Betriebstemperatur | 0C to +85C (Commercial, C suffix) | 0 C to 85 C junction |
| Configuration Memory | On-chip Flash (non-volatile) + SRAM | — |
| Lead-Free / RoHS | Lead Free, RoHS Compliant | — |
| Halogenfrei | Yes (per Lattice MachXO2 family datasheet) | — |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Product Family | — | MachXO2 |
| Logic Cells | — | 1,280 cells |
| LUT Count | — | 1,280 LUTs |
| Available I/O | — | 79 I/O |
| User Memory | — | 256 kbits |
| Dedicated FIFO Control Logic | — | Supported |
| Versorgungsspannung | — | 3.3 V |
| Speed Grade | — | -4 |
| Technology | — | Advanced 65 nm low-power process |
| I/O Feature | — | Programmable low-swing differential I/O |
| Power-Saving Modes | — | Standby mode and other power-saving options |
| Montageart | — | Surface Mount |
| Voltage Variant | — | 2.5 V or 3.3 V external VCC supply for HC family |
| RoHS | — | RoHS listed by the Micros product excerpt |