LTC2314CTS8-14 vs LTC2313HTS8-14 Vergleich
Detaillierter Direktvergleich von LTC2314CTS8-14 von Analog Devices und LTC2313HTS8-14 von Analog Devices. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Analog Devices
LTC2313HTS8-14 - 14-bit 2.5Msps SAR ADC in TSOT-23-8 | Analog Devices
LTC2313HTS8-14 ✓ AktivSpezifikationsvergleich
| Parameter | LTC2314CTS8-14 | LTC2313HTS8-14 |
|---|---|---|
| Marke | Analog Devices | Analog Devices |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,05 | $4,10 |
| Auflösung | 14 bits | 14 bits |
| Sample Rate | 4.5 Msps | 2.5 Msps |
| Architecture | SAR (Successive Approximation Register) | SAR (Successive Approximation Register) |
| Number of Input Channels | 1 | 1 (single-ended/differential) |
| Analog Supply Voltage | 2.7 V to 5.25 V | — |
| Versorgungsstrom | 6.2 mA (typical at 4.5 Msps) | 5 mA at 2.5 Msps |
| Digital I/O Logic Levels | 1.8 V / 2.5 V / 3 V / 5 V | — |
| Serial Interface | SPI-compatible | SPI-compatible SCK/SDO/SDI/CSF, supports 1.8 V/2.5 V/3 V/5 V logic |
| Integrated Reference | Yes - bandgap + reference buffer | — |
| Reference Drift | 20 ppm/°C (maximum) | — |
| Power-Down Modes | Nap and Sleep | — |
| Gehäuse | TSOT-23-8 | TSOT-23-8 (HTS8) |
| Betriebstemperatur | -40 °C to +125 °C [DATA_NEEDED: confirmed from datasheet temperature grade code C] | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes (PBF suffix) | — |
| Versorgungsspannung | — | 3 V to 5 V (single supply, 5 V typical) |
| Input Type | — | Pseudo-differential (IN+, IN-) |
| Internal Reference | — | 2.5 V nominal, 20 ppm/°C max drift |
| No-Missing-Codes Performance | — | 14 bits guaranteed |
| Latency | — | 0 conversion latency |
| Betriebstemperaturbereich | — | -40 °C to +125 °C (H-grade) |
| MSL-Level | — | 1 (per JEDEC J-STD-020) |
| Conversion Cycles | — | 16 SCK per conversion (14-bit plus 2 dummy bits) |