MAX11162ETB+ vs MAX11163ETB+T Vergleich
Detaillierter Direktvergleich von MAX11162ETB+ von Analog Devices und MAX11163ETB+T von Maxim Integrated. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Maxim Integrated
MAX11163ETB+T - 16-Bit 250ksps SAR ADC, 5V Unipolar | Maxim Integrated
MAX11163ETB+T ✓ AktivSpezifikationsvergleich
| Parameter | MAX11162ETB+ | MAX11163ETB+T |
|---|---|---|
| Marke | Analog Devices | Maxim Integrated |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,36 | $4,62 |
| Auflösung | 16 bit | 16 bit |
| Architecture | SAR (Successive Approximation Register) | SAR (Successive Approximation) |
| Number of Channels | 1 single-ended input | 1 |
| Abtastrate | 500 ksps | 250 ksps |
| Analog Supply Voltage | 3 V to 5 V (single supply) | — |
| Digital I/O Supply | 1.8 V to 5 V (VLOGIC, independent of AVDD) | — |
| Input Type | Single-ended, true-differential input stage | — |
| Analog Input Range | 0 V to VREF (unipolar) | — |
| Internal Reference | 2.5 V on-chip bandgap | 4.096 V |
| External Reference Support | Yes (REF pin accepts external reference) | — |
| INL (max) | [DATA_NEEDED: INL max LSB] | ±0.5 LSB |
| SINAD | [DATA_NEEDED: SINAD at fin] | — |
| SFDR | [DATA_NEEDED: SFDR at fin] | — |
| Data Interface | SPI/QSPI/MICROWIRE-compatible serial | — |
| Gehäuse | 10-pin TDFN (3 mm x 3 mm) EP | 10-pin TDFN (3x3 mm) with EP |
| Betriebstemperatur | -40 C to +85 C (industrial) | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant | Compliant |
| Input Configuration | — | Pseudo-Differential, Unipolar |
| Eingangsspannungsbereich | — | 0 V to +5 V (unipolar) |
| Supply Voltage (AVDD) | — | 5 V |
| SNR | — | 92 dB at 10 kHz input |
| Operating Current (typ, 250 ksps) | — | 3.6 mA |
| Betriebstemperaturbereich | — | -40 C to +85 C |
| Conversion Latency | — | 0 (no pipeline delay) |