MC33937APEK574 vs MC33937APEK Vergleich

Detaillierter Direktvergleich von MC33937APEK574 von NXP Semiconductors und MC33937APEK von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

NXP Semiconductors
MC33937APEK574 MC33937APEK574 - 3-Phase FET Pre-Driver, 1.5A Gate, 40V, SPI | NXP

MC33937APEK574 - 3-Phase FET Pre-Driver, 1.5A Gate, 40V, SPI | NXP

MC33937APEK574 ✓ Aktiv
NXP Semiconductors
MC33937APEK MC33937APEK - 3-Phase FET Pre-Driver, 1.5A, 40V, SPI | NXP

MC33937APEK - 3-Phase FET Pre-Driver, 1.5A, 40V, SPI | NXP

MC33937APEK ✗ Abgekündigt

Spezifikationsvergleich

Parameter MC33937APEK574 MC33937APEK
Marke NXP Semiconductors NXP Semiconductors
Kategorie Motor Drivers Motor Drivers
Lebenszyklusstatus Aktiv Ende des Lebenszyklus
Lagerstatus In Stock In Stock
Stückpreis (USD) $3,13 $3,78
Funktion 3-Phase FET Pre-Driver —
Topology Driven Three-phase N-channel MOSFET bridge (6 FETs) —
Peak Gate Drive Current >1.5 A (typ) —
Supply Voltage (VCC / VDD) 40 V max —
Operating VDD [DATA_NEEDED: VDD operating range] —
Bootstrap Supply (VBS) [DATA_NEEDED: VBS voltage range] —
Gate Drive Voltage [DATA_NEEDED: VGS drive voltage] —
Communication Interface SPI (daisy-chain capable) —
Number of Phases 3 —
Number of Channels (HS+LS) 6 (3 high-side + 3 low-side) —
Short-Circuit Protection Desaturation detection (programmable threshold) —
Dead-Time Adjustment Programmable via SPI/external resistor —
Charge Pump Integrated (100% duty-cycle capable) Integrated for high-side gate supply (VLS, VLS_CAP)
Gehäuse 54-SOIC-EP (exposed pad) 54-pin SOIC-EP (exposed pad)
Montageart Surface Mount Surface Mount
Betriebstemperaturbereich [DATA_NEEDED: operating temp range] -40 C to +125 C
MSL-Level [DATA_NEEDED: MSL level] —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 grade] —
Product Type — 3-phase FET pre-driver (gate driver)
Anzahl der Ausgänge — 6 (3 high-side + 3 low-side)
Supply Voltage (Vdd) — 5 V typical logic supply
Battery / VPS Voltage Range — 6 V to 40 V (load-dump tolerant)
Gate Drive Current — greater than 1.5 A peak
Schnittstelle — SPI (Serial Peripheral Interface)
Integrated Protections — FET short-circuit / desaturation, over-current, undervoltage
Ausgangskonfiguration — Three half-bridge gate drivers for external N-channel MOSFETs
Dead-Time Control — Programmable via SPI
Technology — SMARTMOS mixed-signal
Automotive Qualification — AEC-Q100 qualified (per NXP product family page)

Datenblätter & Ressourcen

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