MCIMX31LVMN5C vs MCIMX31LCVMN4C Vergleich
Detaillierter Direktvergleich von MCIMX31LVMN5C von NXP Semiconductors und MCIMX31LCVMN4C von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
MCIMX31LVMN5C - ARM1136JF-S SoC, 532MHz, 473-LFBGA | NXP / Freescale
MCIMX31LVMN5C ✓ AktivNXP Semiconductors
MCIMX31LCVMN4C - i.MX31L ARM1136 400MHz MPU, MAPBGA-457 | NXP
MCIMX31LCVMN4C ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | MCIMX31LVMN5C | MCIMX31LCVMN4C |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Core Architecture | ARM1136JF-S | ARM1136JF-S |
| Core Count | 1 | 1 |
| Datenbusbreite | 32-bit | 16-bit |
| Maximum CPU Clock | 532 MHz | — |
| Operating Voltage - Core | [DATA_NEEDED: core Vdd] | — |
| Operating Voltage - I/O | [DATA_NEEDED: I/O Vdd] | — |
| L1 Instruction Cache | 32 KB | — |
| L1 Data Cache | 32 KB | — |
| Graphics Processing Unit | Not included (i.MX31L variant) | — |
| Image Processing Unit (IPU) | Yes (2D) | Yes |
| MPEG-4 / H.263 Hardware Codec | Yes | — |
| Memory Controller | DDR1 up to 133 MHz, SDRAM, NAND flash | — |
| LCD Controller | Up to SXGA resolution | — |
| Gehäuse | 473-LFBGA (19x19 mm, 0.8 mm pitch) | — |
| Montageart | Surface Mount | Surface Mount |
| Series | i.MX31 / i.MX31L Multimedia Applications Processors | — |
| Manufacturer | Freescale Semiconductor (acquired by NXP) | — |
| RoHS-Status | Compliant | Compliant |
| Vector Floating Point (VFP) | Yes | — |
| Maximale Taktfrequenz | — | 400 MHz |
| Betriebstemperaturbereich | — | -40C to +85C |
| Package Type | — | MAPBGA-457 |
| Package Dimensions | — | 14 x 14 mm |
| Ball Pitch | — | 0.5 mm |
| Pin-Anzahl | — | 457 |
| Family | — | i.MX31L |
| Variant Suffix | — | N4C (industrial/auto temp grade) |
| Process Node | — | [DATA_NEEDED: process node] |
| L1 Cache | — | [DATA_NEEDED: L1 instruction/data cache] |
| L2 Cache | — | [DATA_NEEDED: L2 cache] |
| Integrated LCD Controller | — | Yes |
| USB Interface | — | USB 2.0 with on-chip PHY |
| AEC-Q100 Grade | — | Grade 3 |