MPC8548EPXAQGD vs MPC8548EPXAVHD Vergleich
Detaillierter Direktvergleich von MPC8548EPXAQGD von NXP Semiconductors und MPC8548EPXAVHD von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | MPC8548EPXAQGD | MPC8548EPXAVHD |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $205,00 | $175,50 |
| Core Architecture | PowerPC e500 | — |
| Core Count | 1 | — |
| Datenbusbreite | 32-bit | — |
| Maximum Core Frequency | 1.0 GHz | — |
| Process Technology | 0.09 um CMOS | — |
| Gehäuse | 783-ball FC-PBGA (29x29 mm) | 783-FCPBGA (FCBGA, 29x29 mm) |
| Supply Voltage (Core) | 1.0 V | — |
| Supply Voltage (DDR2 I/O) | 1.8 V | — |
| Supply Voltage (I/O) | 2.5 V / 3.3 V | — |
| Betriebstemperatur | 0 C to +105 C | 0 C to +105 C (TJ, VHD grade) |
| Ethernet | Dual 10/100/1000 Mbps (GMII/RTA/RGMII/TBI) | Gigabit Ethernet (2x, SGMII) |
| PCI Interfaces | 3x PCI/PCI-X + 1x PCIe x8 or Serial RapidIO | — |
| Memory Controller | DDR2 SDRAM with ECC | — |
| Security Engine | SEC 2.0 (IPsec, SSL/TLS, public key) | SEC (AES, DES/3DES, SHA, public key) |
| Local Bus | 64-bit | — |
| DMA Channels | 4 | — |
| Montageart | Surface Mount (FC-PBGA) | Surface Mount (BGA) |
| RoHS-Status | Compliant (per NXP product page) | [DATA_NEEDED: RoHS status] |
| Core Processor | — | PowerPC e500 |
| Number of Cores | — | 1 |
| Bus Width | — | 32-Bit |
| Core Frequency | — | 1.5 GHz |
| Series | — | MPC85xx (PowerQUICC III) |
| Co-Processors / DSP | — | Signal Processing Engine (SPE); Security Engine (SEC) |
| RAM Controllers | — | DDR, DDR2, SDRAM |
| Graphics Acceleration | — | No |
| PCI / PCI-X | — | PCI-X supported |
| PCI Express | — | Yes (3x PCIe interfaces) |
| Serial RapidIO | — | Yes (4x SRIO lanes) |
| Silicon Revision | — | R3 |