MPC8548EVTAVHD557 vs MPC8548EVTAVHD Vergleich

Detaillierter Direktvergleich von MPC8548EVTAVHD557 von NXP Semiconductors und MPC8548EVTAVHD von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

NXP Semiconductors
MPC8548EVTAVHD557 MPC8548EVTAVHD557 - PowerQUICC III e500 SoC 1.5GHz | NXP

MPC8548EVTAVHD557 - PowerQUICC III e500 SoC 1.5GHz | NXP

MPC8548EVTAVHD557 Nrnd
NXP Semiconductors
MPC8548EVTAVHD MPC8548EVTAVHD - PowerQUICC III 1.5GHz SoC MPU | NXP

MPC8548EVTAVHD - PowerQUICC III 1.5GHz SoC MPU | NXP

MPC8548EVTAVHD ✓ Aktiv

Spezifikationsvergleich

Parameter MPC8548EVTAVHD557 MPC8548EVTAVHD
Marke NXP Semiconductors NXP Semiconductors
Kategorie Microcontrollers Microcontrollers
Lebenszyklusstatus NRND Aktiv
Family PowerQUICC III (MPC85xx) —
Core Power Architecture e500, 32-bit —
Core Frequency 1.5 GHz —
Instruction Set Power Architecture Book E + signal-processing engine —
FPU Double-precision hardware FPU —
L1 Cache 32 KB instruction + 32 KB data 32 KB I-cache + 32 KB D-cache
L2 Cache [DATA_NEEDED: L2 cache size] 512 KB unified on-chip
Security Engine SEC 2.0 (IPsec, SSL/TLS, 3DES, AES, SHA, RSA, ECC) SEC 2.0 (AES, DES, 3DES, Kasumi, SHA, MD5, public-key)
Gigabit Ethernet 3x 10/100/1000 enhanced GETH with SGMII / RGMII / RTBI —
PCI Express 2x PCIe interfaces (x1/x2/x4 capable) 2x PCIe interfaces
Serial RapidIO 2x SRIO ports (1x/4x lane) 2x SRIO ports
DDR Memory Controller 2x 64-bit DDR2 with ECC, up to 533 MHz —
PCI / PCI-X 2x 64-bit PCI / PCI-X controllers 2x 64-bit PCI/PCI-X
Local Bus 8-bit / 16-bit / 32-bit Local Bus + GPIO —
Serial I/O 4x I2C, 2x UART, DUART, SPI —
Betriebstemperatur 0 C to +105 C (extended) 0C to +105C
Versorgungsspannung 1.0 V core / 1.5 V DDR / 1.8 V / 2.5 V / 3.3 V I/O —
Gehäuse 783-ball FCBGA, 29x29 mm 783-FCBGA (29x29 mm)
Process Node 90 nm CMOS —
RoHS-Status Compliant (lead-free FCBGA) [DATA_NEEDED: rohs status]
Series — PowerQUICC III
Core Architecture — Power Architecture e500 v2
Core Count — 1
Bit Width — 32-bit
Maximum CPU Clock — 1.5 GHz
Process Technology — 0.09 um CMOS
Memory Controller — 64-bit DDR2 SDRAM with ECC, up to 533 MT/s
Ethernet — 4x Gigabit Ethernet (SGMII/RGMII/TBI/RTBI)
Betriebsversorgungsspannung — 1.8 V / 2.5 V / 3.3 V
Montageart — Surface Mount
Silicon Revision — R3

Datenblätter & Ressourcen

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