MSC8156ESAG1000B vs MSC8157TAG1000A Vergleich
Detaillierter Direktvergleich von MSC8156ESAG1000B von NXP Semiconductors und MSC8157TAG1000A von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
MSC8156ESAG1000B - 6x SC3850 1GHz DSP SoC | NXP Semiconductors
MSC8156ESAG1000B ✗ AbgekündigtNXP Semiconductors
MSC8157TAG1000A - 6-Core SC3850 DSP, 1GHz, MAPLE-B2 | NXP
MSC8157TAG1000A ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | MSC8156ESAG1000B | MSC8157TAG1000A |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | DSP | DSP |
| Lebenszyklusstatus | Ende des Lebenszyklus | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $112,00 | $178,00 |
| DSP Cores | 6x SC3850 StarCore cores | — |
| Core Clock Frequency | 1 GHz per core | — |
| Aggregate Performance | [DATA_NEEDED: aggregate MMACS rating] | — |
| Process Technology | 45 nm CMOS | — |
| Hardware Accelerator | MAPLE-B baseband accelerator (turbo decode) | — |
| Memory Controller | 64-bit DDR2/DDR3, up to 800 MT/s | Dual-channel DDR2/DDR3 with ECC |
| SerDes Lanes | 2 lanes, SRIO or PCIe (selectable) | — |
| Ethernet | 1x Gigabit Ethernet MAC | — |
| Packet Engine | QUICC Engine subsystem | — |
| Security Engine | SEC 4.0 (Cryptographic accelerator) | — |
| Gehäuse | 783-ball FCBGA (29x29 mm) | 783-FCPBGA (29x29 mm) |
| Betriebstemperatur | 0C to +105C | -40C to +105C |
| Versorgungsspannung | [DATA_NEEDED: core and I/O rail voltages] | [DATA_NEEDED: core/IO voltage] |
| Montageart | Surface Mount (BGA) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED] |
| Lebenszyklusstatus | End of Life (per NXP PCN) | — |
| Device Type | — | Six-core Digital Signal Processor (DSP) |
| DSP Architecture | — | StarCore SC3850 (6x cores) |
| Core Frequency | — | 1 GHz per core |
| L1 Instruction Cache | — | 32 KB per core |
| L1 Data Cache | — | 32 KB per core |
| Unified L2 Cache | — | 512 KB (configurable as M2 in 64 KB increments) |
| Accelerator | — | MAPLE-B2 baseband accelerator |
| High-Speed Serial I/O | — | 2x SRIO, 2x PCIe, 2x GbE, 2x CIPRI |
| Ball Pitch | — | 1.0 mm |
| MMU | — | Yes |
| Interrupt Controller | — | EPIC (Extended Programmable Interrupt Controller) |
| Timers | — | 2x 32-bit general-purpose per core |
| MSL-Level | — | [DATA_NEEDED] |