P5010NSN1QMB557 vs P5010NSN1QMB Vergleich
Detaillierter Direktvergleich von P5010NSN1QMB557 von NXP Semiconductors und P5010NSN1QMB von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
P5010NSN1QMB - QorIQ P5010 SoC, 64-bit Power Arch, 2.0GHz, 1295-FCBGA | NXP
P5010NSN1QMB ✓ AktivSpezifikationsvergleich
| Parameter | P5010NSN1QMB557 | P5010NSN1QMB |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $198,00 | $318,25 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | QorIQ P5 | — |
| Core Processor | PowerPC e5500 | — |
| Number of Cores | 1 | — |
| Core Architecture | 64-bit Power Architecture | — |
| Core Speed | 2.0 GHz | — |
| Gehäuse / Bauform | 1295-BBGA, FCBGA | — |
| Supplier Device Package | 1295-FCPBGA (37.5 x 37.5 mm) | — |
| Montageart | Surface Mount | — |
| Betriebstemperatur | 0C to 105C (TA) | 0C to +105C |
| Product Status | Active | — |
| Terminal Form | Ball | — |
| Number of Terminals | 1295 | — |
| Package Code | BGA | — |
| Memory Controller | Dual DDR3 with ECC [DATA_NEEDED: data rate] | DDR3 with ECC support |
| Security Engine | SEC 4.0 (DES/3DES/AES/SHA) [DATA_NEEDED: throughput] | SEC crypto engine integrated |
| RoHS-Status | [DATA_NEEDED: rohs status from datasheet] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | — | Power Architecture e5500 (64-bit) |
| Core Count | — | 1 core |
| Maximum Core Frequency | — | 2.0 GHz |
| Cache (L1 Instruction per core) | — | 32 KB |
| Cache (L1 Data per core) | — | 32 KB |
| Cache (L2 shared frontside) | — | 1 MB |
| PCIe | — | PCI Express Gen 2 controllers integrated |
| Ethernet | — | Dual Gigabit Ethernet |
| High-Speed Interconnect | — | Serial RapidIO (SRIO) |
| Hardware Acceleration | — | DPAA (Data Path Acceleration Architecture) engine |
| Gehäuse | — | 1295-FCBGA (37.5 x 37.5 mm) |
| Encryption | — | Hardware-accelerated |