P5010NXN1QMB557 vs P5010NXE1QMB557 Vergleich
Detaillierter Direktvergleich von P5010NXN1QMB557 von NXP Semiconductors und P5010NXE1QMB557 von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
P5010NXN1QMB557 - QorIQ P5 2GHz 64-Bit MPU | NXP 1295-FCPBGA
P5010NXN1QMB557 ✓ AktivNXP Semiconductors
P5010NXE1QMB557 - QorIQ P5010 e5500 SoC 1.6GHz FC-PBGA-1295 | NXP
P5010NXE1QMB557 ✓ AktivSpezifikationsvergleich
| Parameter | P5010NXN1QMB557 | P5010NXE1QMB557 |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $129,60 | $205,00 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | QorIQ P5 | — |
| Core Architecture | PowerPC e5500, 64-bit | Power Architecture e5500, 64-bit |
| Number of Cores | 1 | 1 |
| Maximum Core Frequency | 2.0 GHz | 1.6 GHz (1600 MHz) |
| External Data Bus Width | 64-bit | — |
| Address Bus Width | 16-bit (per Microchip USA listing) | — |
| Gehäuse | 1295-ball FCPBGA (37.5 x 37.5 mm) | 1295-ball FC-PBGA (37.5x37.5 mm) |
| Ball Pitch | 1.00 mm | 1.00 mm |
| JESD-30 Package Code | S-PBGA-B1295 | — |
| Process Technology | CMOS | — |
| Integrated Cache | Yes (L1 + L2) | — |
| Low-Power Mode Support | Yes | — |
| RoHS-Status | Compliant | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +105C (extended) |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Family | — | QorIQ P5 |
| Secondary Core Frequency | — | 1.2 GHz (1200 MHz, r2.0) |
| L1 I-Cache per Core | — | 32 KB |
| L1 D-Cache per Core | — | 32 KB |
| Memory Controller | — | DDR3/DDR3L with ECC |
| PCIe Lanes | — | Yes |
| Serial RapidIO (SRIO) | — | Yes |
| Gigabit Ethernet | — | Yes (multiple SerDes lanes) |
| Security Engine (SEC) | — | Integrated |
| Hardware Acceleration | — | Integrated |
| Boundary Scan | — | Yes (IEEE 1149.1/JTAG) |