RTAX2000D-1CQ352E vs RTAX2000D-1CQ352B Vergleich
Detaillierter Direktvergleich von RTAX2000D-1CQ352E von Microchip Technology und RTAX2000D-1CQ352B von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
RTAX2000D-1CQ352E - 2M-Gate Rad-Tolerant FPGA CQFP352 | Microchip
RTAX2000D-1CQ352E ✓ AktivMicrochip Technology
RTAX2000D-1CQ352B - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000D-1CQ352B ✓ AktivSpezifikationsvergleich
| Parameter | RTAX2000D-1CQ352E | RTAX2000D-1CQ352B |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3.650,00 | $3.120,00 |
| Equivalent System Gates | 2000000 gates | 2,000,000 |
| Logic Organization | 19712 CLBs | — |
| Technology | Digital CMOS FPGA, antifuse (nonvolatile) | Antifuse (nonvolatile), Digital CMOS |
| Gehäuse | CQFP352 (352-terminal Ceramic Quad Flat Pack) | 352-pin Ceramic Column Grid Array (CQ352) |
| Betriebstemperaturbereich | -55C to +125C | — |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | RTAX-S/SL and RTAX-DSP (RTAX2000D) |
| Total Ionizing Dose (Functional) | 300 krad | — |
| Total Ionizing Dose (Rated) | 200 krad | — |
| DSP Mathblocks | Up to 120 | Up to 120 (18-bit x 18-bit MAC) |
| DSP MAC Performance | 125 MHz, 18-bit x 18-bit multiply-accumulate | — |
| Embedded Memory | Up to 540 kbits with optional EDAC protection | Up to 540 kbits SRAM with optional EDAC |
| Programmability | One-time programmable (antifuse) | — |
| Versorgungsspannung | [DATA_NEEDED: core/supply voltage] | — |
| User I/O Terminals | [DATA_NEEDED: user I/O count for CQ352] | — |
| Max System Frequency | [DATA_NEEDED: max system frequency] | — |
| Radiation Environment Target | Space-based applications | — |
| Commercial Prototype Equivalent | Axcelerator family device | — |
| CLBs (Logic Cells) | — | 19,712 CLBs / 29,568 logic cells (per family organization) |
| DSP Performance | — | 125 MHz 18-bit x 18-bit multiply-accumulate |
| Total Ionizing Dose | — | 300 krad (Si) functional / 200 krad (Si) with operation |
| Core Supply Voltage | — | 1.5 V nominal (1.425 V to 1.575 V) |
| Speed Grade | — | -1 |
| Temperature Range | — | Commercial (C) |
| Configuration | — | Live at power-up, no external configuration device (antifuse) |
| Routing Features | — | Segmentable clocks, chip-wide highway routing, carry logic |
| Embedded SRAM Features | — | Built-in FIFO control logic |
| Montageart | — | Surface Mount (ceramic column grid array) |
| Application Domain | — | Space-flight, radiation-tolerant |