RTAX250S-CG624EV vs RTAX250SL-CG624E Vergleich
Detaillierter Direktvergleich von RTAX250S-CG624EV von Microchip Technology und RTAX250SL-CG624E von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
RTAX250S-CG624EV - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250S-CG624EV ✓ AktivMicrochip Technology
RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624E ✓ AktivSpezifikationsvergleich
| Parameter | RTAX250S-CG624EV | RTAX250SL-CG624E |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $1.375,00 |
| System Gates | 250000 gates | 250000 |
| Logic Cells | 4224 cells | — |
| Configurable Logic Blocks (CLBs) | 2816 | — |
| Maximale Taktfrequenz | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Package Type | 624-pin Ceramic Grid Array (CGA/CCGA) | — |
| Pin-Anzahl | 624 | — |
| Betriebstemperatur | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | CMOS |
| Radiation Tolerance | SEU-hardened registers; SEU rate < 10-10 errors per bit-day | SEU-hardened registers; SEU rate < 10-10 errors/bit-day |
| SEU Immunity | [DATA_NEEDED: LET threshold (MeV-cm2/mg)] | — |
| Configuration | Anti-fuse, live-at-power-up, single chip | — |
| Montageart | Surface Mount (ceramic column grid array) | Surface Mount |
| Family | RTAX-S RadTolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Cells (CLBs) | — | 2816 |
| Maximum Frequency | — | 649 MHz |
| Supply Voltage Tolerance | — | +/-0.15 V |
| Maximum Combinatorial Delay | — | 0.93 ns |
| Gehäuse | — | 624-Pin CCGA (Ceramic Column Grid Array) |
| Embedded Memory | — | Embedded SRAM with built-in FIFO control logic |
| Clocking | — | Segmentable clocks, chip-wide highway routing |
| Programmability | — | Live at power-up, true single-chip |