XC3090L-125PC84C vs XC3090L-8PCG84C Vergleich
Detaillierter Direktvergleich von XC3090L-125PC84C von Xilinx und XC3090L-8PCG84C von Xilinx. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Xilinx
XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family
XC3090L-8PCG84C ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | XC3090L-125PC84C | XC3090L-8PCG84C |
|---|---|---|
| Marke | Xilinx | Xilinx |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $64,00 | $26,10 |
| Manufacturer | Xilinx | — |
| Series | XC3000L | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Logic Family | XC3000L Low-Voltage Logic Cell Array | — |
| Process Technology | CMOS, SRAM-based | [DATA_NEEDED: process node] |
| Configurable Logic Blocks (CLBs) | 320 | — |
| Equivalent Gates | ~5,000 | — |
| Flip-Flops | 928 | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Betriebstemperatur | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] | 0 C to +70 C (commercial 'C' suffix) |
| Gehäuse | 84-pin PLCC (J-lead, package code QCCJ) | 84-pin PLCC (J-Lead, PCG84) |
| Terminal Form | J-BEND (J-lead) | — |
| Montageart | Surface Mount | Surface Mount (PLCC J-Lead) |
| Configuration Interface | Serial/parallel mode, JTAG (IEEE 1149.1) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Family | — | XC3000A/L Series FPGA |
| Logic Cells / CLBs | — | 70 Configurable Logic Blocks |
| Gate Count | — | 6,400 gates (typical) |
| Configuration Program Store | — | 64,160 bits |
| User I/O Pins | — | 70 (maximum) |
| Speed Grade | — | -8 (moderate) |
| Configuration Modes | — | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Configuration Clock Range | — | [DATA_NEEDED: CCLK frequency range] |
| Lead-Free | — | unknown |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Programming Technology | — | SRAM-based, in-system reconfigurable |