XC3090L-6TQ176I vs XC3090L-6TQG176C Vergleich
Detaillierter Direktvergleich von XC3090L-6TQ176I von Xilinx und XC3090L-6TQG176C von Xilinx. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | XC3090L-6TQ176I | XC3090L-6TQG176C |
|---|---|---|
| Marke | Xilinx | Xilinx |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $140,00 | $63,00 |
| Family | XC3000L Low Voltage Logic Cell Array | XC3000L Low-Voltage Logic Cell Array |
| Logic Cells | [DATA_NEEDED: logic cell count] | — |
| Maximum User I/O | 100 | — |
| Number of I/O Banks | 4 | — |
| Configuration Memory | SRAM (volatile, external PROM required) | SRAM (volatile, in-system programmable) |
| Speed Grade | -6 | -6 (6 ns tpd) |
| Combinatorial Logic Performance | up to 320 MHz | — |
| Gehäuse | TQFP-176 (TQ176) | TQG176 (Thin Quad Gull-Wing, 176 pins) |
| Lead Pitch | 0.5 mm | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | -40C to +85C (industrial, I suffix) | — |
| Core Voltage | [DATA_NEEDED: VCCINT] | — |
| I/O Voltage | [DATA_NEEDED: VCCIO] | — |
| Configuration Interface | Serial mode (master/slave), JTAG | — |
| MSL-Level | [DATA_NEEDED: MSL] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown (legacy family, pre-dates RoHS documentation conventions) |
| Lifecycle | Obsolete (XC3000L family) | — |
| Series | — | XC3000L |
| Device | — | XC3090L |
| User I/O Count | — | 138 |
| Versorgungsspannung | — | 3.3 V |
| Combinatorial Logic Delay (tpd) | — | 6 ns |
| Betriebstemperatur | — | Commercial (0C to +70C) |
| Family Differentiator | — | Low-voltage 3.3V core vs 5.0V XC3000A |
| Compatible Programming Tools | — | Xilinx XChecker, JTAG boundary-scan, PROM-based serial configuration |
| Lead Free | — | unknown |
| Pinout Type | — | Perimeter I/O ring with user I/O and dedicated configuration pins |