XC3090L-6TQG176C vs XC3090L-7TQG176C Vergleich
Detaillierter Direktvergleich von XC3090L-6TQG176C von Xilinx und XC3090L-7TQG176C von Xilinx. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | XC3090L-6TQG176C | XC3090L-7TQG176C |
|---|---|---|
| Marke | Xilinx | Xilinx |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $63,00 | $21,20 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000L |
| Series | XC3000L | — |
| Device | XC3090L | XC3090L |
| Speed Grade | -6 (6 ns tpd) | — |
| User I/O Count | 138 | 144 (maximum, TQG176) |
| Gehäuse | TQG176 (Thin Quad Gull-Wing, 176 pins) | 176-pin TQFP (TQG176), 1.4 mm height, surface-mount |
| Versorgungsspannung | 3.3 V | — |
| Combinatorial Logic Delay (tpd) | 6 ns | — |
| Configuration Memory | SRAM (volatile, in-system programmable) | SRAM (volatile, requires external PROM) |
| Betriebstemperatur | Commercial (0C to +70C) | — |
| Montageart | Surface Mount | Surface Mount |
| Family Differentiator | Low-voltage 3.3V core vs 5.0V XC3000A | — |
| Compatible Programming Tools | Xilinx XChecker, JTAG boundary-scan, PROM-based serial configuration | — |
| RoHS-Status | unknown (legacy family, pre-dates RoHS documentation conventions) | unknown |
| Lead Free | unknown | — |
| Pinout Type | Perimeter I/O ring with user I/O and dedicated configuration pins | — |
| Logic Cells / CLBs | — | 100 CLBs (320 F-FFs) |
| Usable Gates | — | 5,000 (typical, up to 9,000 peak) |
| Process Technology | — | 0.8 micron CMOS |
| Supply Voltage (Core) | — | 3.0 V to 3.6 V |
| Supply Voltage (I/O VCCO) | — | 3.0 V to 3.6 V |
| Logic Cell Toggle Delay | — | approximately 1.3 to 1.5 ns (-7 speed grade) |
| Betriebstemperaturbereich | — | 0C to +85C (C suffix, commercial) |
| Configuration Mode | — | Serial (master/slave) and JTAG (IEEE 1149.1) |
| MSL-Level | — | 3 (168 hours) [DATA_NEEDED: confirm per package marking] |
| Lead-Free / Lead Content | — | [DATA_NEEDED] |
| Configuration Clock Source | — | Internal oscillator amplifier or external pin |
| Output Drive (per I/O) | — | 8 mA source / 24 mA sink (typical, datasheet TBD by speed grade) |