AD9609BCPZ-80 - 10-Bit 80 MSPS 1.8V ADC | Analog Devices
Teilenummer: AD9609BCPZ-80 ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.4 | $164,00 |
| 100 | $14.2 | $1.420,00 |
| 500 | $12.1 | $6.050,00 |
| 1.000 | $10.4 | $10.400,00 |
AD9609BCPZ-80 Übersicht
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a defined sampling rate, forming the critical interface between the analog sensor/frontend world and the digital signal-processing world. Within the data-converter hierarchy the AD9609BCPZ-80 sits under pipeline ADC -> high-speed ADC -> data converter -> mixed-signal IC -> semiconductor. Pipeline ADCs use multiple low-resolution stages to achieve high sample rates with moderate power consumption, making them standard in communications infrastructure, radar, imaging, and industrial instrumentation where tens-of-MHz to low-GHz analog bandwidths must be digitized.
Key features include SPI/serial-port control for flexible configuration, single-ended or differential analog inputs with selectable input ranges, an on-chip 1.0 V reference (with external-reference option), a power-down mode controlled via the SDIO/PDWN pin, and a CMOS-compatible output bus configurable as either parallel or serial (one-pair) LVDS. The combination of a 1.8 V analog core and 3.3 V digital I/O simplifies interfacing to FPGAs, ASICs, and DSPs that require 3.3 V logic-level outputs without level shifters. Operating temperature range spans -40 °C to +85 °C, suiting industrial environments.
The 32-lead LFCSP-VQ (5x5 mm) package provides a low-inductance ground/thermal path through the exposed pad and is pin-compatible with the AD9629 (12-bit, 20/40/65/80 MSPS) and the AD9649 (14-bit, 20/40/65/80 MSPS) families. This enables a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS, allowing board reuse across different resolution nodes with no PCB rework.
Typical applications include low-cost digital oscilloscopes, portable instrumentation, software-defined radios, IF sampling in communications receivers, medical imaging front-ends, and industrial ultrasound. The wide input bandwidth and high SFDR make it suitable for digitizing intermediate-frequency (IF) signals in single- or multi-carrier systems where spurious-free dynamic range dominates the link-budget calculation.
When designing with the AD9609BCPZ-80, observe the ADI recommended anti-alias filter topology at the analog input, route the analog and digital supplies with separate ferrite beads, and bond the exposed pad to a low-impedance ground plane that is at least 4-6 vias for thermal relief. Decouple each supply pin with a 0.1 µF ceramic capacitor placed within 1-2 mm of the pin, and add a 10 µF bulk capacitor nearby.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, application-grade design notes, and a side-by-side comparison table with the AD9629 and AD9649 families that is not found in the manufacturer datasheet alone.
Drop-in-Alternativen für AD9609BCPZ-80 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit AD9609BCPZ-80 (gleiche Bauform und Footprint) – abweichend in Input Type, Operating Temperature Range, Package, Architecture, Number of Channels.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
AD9609BCPZ-65
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9609BCPZ-40
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9629BCPZ-80
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9649BCPZ-80
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9649BCPZ-65
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9609BCPZ-80 Grenzwerte & elektrische Eigenschaften
| Number of Bits | 10 bit |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Abtastrate | 80 MSPS |
| Sampling Rate (Family Options) | 20 / 40 / 65 / 80 MSPS (selected by part suffix) |
| Analog Supply Voltage | 1.8 V |
| Digital Output Supply | 3.3 V |
| Input Type | Single-ended / differential |
| Data Interface | Serial, SPI™ control port; parallel or 1-pair LVDS data output |
| On-chip Reference | Yes (1.0 V typical, external-reference option) |
| SNR (fIN = 9.7 MHz) | 61.5 dBFS |
| SNR (fIN = 200 MHz) | 61.0 dBFS |
| SFDR (fIN = 9.7 MHz) | 75 dBc |
| SFDR (fIN = 200 MHz) | 73 dBc |
| Betriebstemperaturbereich | -40 °C to +85 °C |
| Gehäuse | 32-LFCSP-VQ (5x5 mm) with exposed pad |
| Montageart | Surface Mount |
| Power-Down Pin | SDIO/PDWN (CMOS-compatible) |
| Pin Compatibility | Pin-compatible with AD9629 (12-bit) and AD9649 (14-bit) families |
| RoHS-Status | Compliant |
| Packaging (Shipping) | Tray |
AD9609BCPZ-80 Pin-Konfiguration
| Pin 1 | VIN+ — Differential analog input (positive) |
| Pin 2 | VIN- — Differential analog input (negative) |
| Pin 3 | AVDD — 1.8 V analog supply |
| Pin 4 | AVSS — Analog ground |
| Pin 5 | CML — Common-mode level output (decouple to AVSS) |
| Pin 6 | VREF — Voltage reference I/O (decouple to AVSS) |
| Pin 7 | SENSE — Reference mode select |
| Pin 8 | DRVDD — 3.3 V digital output supply |
| Pin 9 | DRVSS — Digital output ground |
| Pin 10 | D0 — Data output bit 0 (LSB, parallel mode) |
| Pin 11 | D1 — Data output bit 1 (parallel mode) |
| Pin 12 | D2 — Data output bit 2 (parallel mode) |
| Pin 13 | D3 — Data output bit 3 (parallel mode) |
| Pin 14 | D4 — Data output bit 4 (parallel mode) |
| Pin 15 | D5 — Data output bit 5 (parallel mode) |
| Pin 16 | D6 — Data output bit 6 (parallel mode) |
| Pin 17 | D7 — Data output bit 7 (parallel mode) |
| Pin 18 | D8 — Data output bit 8 (parallel mode) |
| Pin 19 | D9 — Data output bit 9 (MSB, parallel mode) |
| Pin 20 | DCO — Data clock output (DDR or SDR per DFS) |
| Pin 21 | OR — Out-of-range indicator |
| Pin 22 | DFS — Data format select / SCLK (SPI) |
| Pin 23 | SDIO/PDWN — Serial data I/O / power-down (SPI) |
| Pin 24 | CSB — SPI chip-select (active low) |
| Pin 25 | CLK+ — Differential sample clock (positive) |
| Pin 26 | CLK- — Differential sample clock (negative) |
| Pin 27 | AVDD — 1.8 V analog supply (second pin) |
| Pin 28 | AVSS — Analog ground (second pin) |
| Pin 29 | AVSS — Analog ground (third pin) |
| Pin 30 | AVDD — 1.8 V analog supply (third pin) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | EP — Exposed pad - bond to AVSS with low-impedance thermal/ground path |
Typische Anwendungen
AD9609BCPZ-80 ist geeignet für 6 Anwendungs: Software-Defined Radio (SDR) IF Sampling, Low-Cost Digital Oscilloscope Front-End, Industrial Ultrasound Imaging Receiver, Medical Imaging Front-End, Communications Receiver IF Digitizing, Portable Instrumentation and Data Acquisition.
Software-Defined Radio (SDR) IF Sampling
The AD9609BCPZ-80 is well-suited for narrow-band IF sampling in software-defined radio receivers. According to the Analog Devices AD9609 datasheet, the converter delivers 61.0 dBFS SNR and 73 dBc SFDR at 200 MHz input, which preserves sufficient spurious-free dynamic range for narrow-band demodulation after digital filtering. The 10-bit resolution is enough for 50-55 dB of usable dynamic range in many IF chains, and the 3.3 V digital supply lets the parallel data bus drive an FPGA directly. Placed between the IF mixer and the FPGA baseband processor, the AD9609BCPZ-80 digitizes 10-100 MHz IF blocks at 80 MSGS without an external downconverter, reducing the analog frontend complexity. The pin-compatible AD9629B (12-bit) and AD9649B (14-bit) provide headroom for migration to wider-bandwidth SDR designs.
Empfohlen
Low-Cost Digital Oscilloscope Front-End
The AD9609BCPZ-80 targets low-cost digital oscilloscope front-ends sampling at 80 MSGS per channel. According to the Analog Devices datasheet, the 10-bit ENOB combined with 200 MHz analog input bandwidth allows entry-level scope designs to digitize a 20 MHz full-scale signal with acceptable small-signal fidelity. The 1.8 V analog / 3.3 V digital supplies simplify the analog input termination network, and the on-chip 1.0 V reference eliminates an external reference part, reducing BOM cost. Used at the heart of a 2-channel scope, multiple AD9609BCPZ-80 devices can be clocked from the same ADF4350 source for coherent sampling. The 32-LFCSP-VQ (5x5 mm) footprint fits in compact handheld scope designs without crowding the input attenuator stage.
Empfohlen
Industrial Ultrasound Imaging Receiver
The AD9609BCPZ-80 is appropriate for industrial ultrasound receiver channels digitizing at 80 MSGS. According to the Analog Devices datasheet, the 10-bit resolution and 75 dBc SFDR at 9.7 MHz allow the part to capture RF echoes in the 5-15 MHz transducer band with sufficient contrast resolution for flaw-detection algorithms. Its 1.8 V core supply keeps channel power low, enabling dense multi-channel receiver arrays. Placed at the output of a time-gain-compensation (TGC) LNA like the AD604, the ADC digitizes the conditioned echo envelope directly. The 32-LFCSP-VQ footprint lets designers place the ADC close to the transducer connector to minimize analog-input trace length, which is critical for SFDR preservation.
Empfohlen
Medical Imaging Front-End
The AD9609BCPZ-80 is suitable for medical imaging front-ends such as optical coherence tomography (OCT) or low-end ultrasound carts. Per the Analog Devices AD9609 datasheet, the converter's 61.5 dBFS SNR at 9.7 MHz input and 200 MHz analog input bandwidth are sufficient for digitizing the OCT interferometric signal envelope in real time at 80 MSGS. The 1.8 V analog / 3.3 V digital supplies simplify the analog signal chain, and the on-chip reference minimizes drift over the -40 °C to +85 °C operating range. Used downstream of a photodiode transimpedance amplifier, the AD9609BCPZ-80 converts the analog depth-scan signal directly into the digital signal-processing FPGA. The 32-LFCSP-VQ package with exposed pad provides good thermal dissipation for back-to-back multi-channel OCT engines.
Empfohlen
Communications Receiver IF Digitizing
The AD9609BCPZ-80 works well for IF sampling in narrow-band communications receivers where the IF falls within 10-200 MHz. According to the Analog Devices datasheet, the device maintains 61.0 dBFS SNR and 73 dBc SFDR at 200 MHz input, which is enough spurious-free dynamic range for single-carrier IF demodulation after digital downconversion. The part's parallel CMOS output mode simplifies connection to a baseband ASIC or FPGA, and the SPI control port allows per-channel gain and phase trim via on-chip registers. Placed between the IF SAW filter and the digital baseband, the AD9609BCPZ-80 enables direct conversion of IF to digital samples at 80 MSGS. The same PCB can later host AD9629B or AD9649B for higher-resolution SDR receivers, because all three are pin-compatible in the 32-LFCSP-VQ footprint.
Empfohlen
Portable Instrumentation and Data Acquisition
The AD9609BCPZ-80 fits portable battery-powered data-acquisition modules that need 10-bit 80 MSGS performance in a small footprint. According to the Analog Devices datasheet, the 1.8 V analog supply keeps power consumption low (typically around 90 mW at 80 MSGS), which extends battery life in handheld instruments. The on-chip voltage reference eliminates an external reference IC, and the CMOS output mode reduces digital output power compared to LVDS, helping total platform power stay low. Deployed between a sensor amplifier chain and an FPGA digital-processing block, the ADC digitizes the conditioned sensor signal at 80 MSGS. The -40 °C to +85 °C operating range and the 32-LFCSP-VQ surface-mount package suit compact handheld instrumentation layouts.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für AD9609BCPZ-80 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | AD9609BCPZ-65 | AD9609BCPZ-40 | AD9629BCPZ-80 | AD9649BCPZ-80 | AD9649BCPZ-65 |
|---|---|---|---|---|---|---|
| Package | 32-LFCSP-VQ (5x5 mm) | 32-LFCSP-VQ (5x5 mm) - same | 32-LFCSP-VQ (5x5 mm) - same | 32-LFCSP-VQ (5x5 mm) - same | 32-LFCSP-VQ (5x5 mm) - same | 32-LFCSP-VQ (5x5 mm) - same |
| Brand | Analog Devices | Analog Devices - same | Analog Devices - same | Analog Devices - same | Analog Devices - same | Analog Devices - same |
| Resolution | 10 bit | 10 bit - same | 10 bit - same | 12 bit (+20%) | 14 bit (+40%) | 14 bit (+40%) |
| Sample Rate | 80 MSPS | 65 MSPS (-19%) | 40 MSPS (-50%) | 80 MSPS - same | 80 MSPS - same | 65 MSPS (-19%) |
| Pin Compatible (Same 32-LFCSP-VQ) | Yes (reference part) | Yes - same family | Yes - same family | Yes - per ADI family doc | Yes - per ADI family doc | Yes - per ADI family doc |
| Analog Supply | 1.8 V | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same |
| Digital Output Supply | 3.3 V | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same |
| Pin Count | 32 pins | 32 - same | 32 - same | 32 - same | 32 - same | 32 - same |
Wichtigste Unterscheidungsmerkmale
- Pin-compatible with AD9629 (12-bit) and AD9649 (14-bit) for simple resolution migration (vs. AD9629BCPZ-80)
- Lower cost than 12-bit and 14-bit pin-compatible alternatives (vs. AD9649BCPZ-80)
- Highest sample rate in the 10-bit AD9609 family (vs. AD9609BCPZ-65)
Designhinweise
Place all decoupling capacitors (0.1 µF ceramic plus 10 µF bulk) within 1-2 mm of each AVDD and DRVDD pin. Per ADI recommendation, bond the LFCSP exposed pad (pin 32) directly to a low-impedance AVSS ground plane with at least 4-6 thermal vias to inner ground layers. Route AVDD with a separate ferrite bead from DRVDD to isolate analog and digital switching return currents - this prevents digital noise from coupling back into the analog reference and degrading SNR.
Use a differential sample clock (CLK+ / CLK-) from a low-jitter PLL such as the ADF4350; single-ended clocks degrade aperture jitter and reduce ENOB. According to the Analog Devices AD9609 datasheet, the input common-mode voltage should be biased to mid-CML (pin 5 decoupled with 0.1 µF to AVSS) and the input driven through a transformer or ADC driver like the AD8476 to preserve SFDR at 200 MHz IF inputs. Avoid long input traces - keep the analog input path under 5 mm and guard both sides with AVSS copper.
The AD9609BCPZ-80 draws approximately 90 mW typical from the 1.8 V analog supply at 80 MSPS. Estimated: at AVDD = 1.8 V and I_AVDD ≈ 50 mA, AVDD power ≈ 0.09 W. Provide at least 200 mA of headroom from the LDO when designing the supply chain, and add a 10 µF bulk capacitor near the AVDD pin to handle transient current during sample transitions. Avoid placing the LDO more than 25 mm from the AVDD pin to prevent IR drop on the 1.8 V rail.
Do not leave the CML and VREF pins floating - they must each be decoupled to AVSS with at least 0.1 µF. Floating the CML pin causes common-mode drift on the analog input stage and reduces SFDR by 5-10 dBc. The SDIO/PDWN pin doubles as both power-down control and SPI data - it must be held at logic-high during power-up if SPI control is not used, otherwise the part enters power-down at startup and outputs no data. The exposed pad (pin 32) MUST be soldered for both electrical ground and thermal relief; missing thermal pad solder can raise junction temperature 15-20 °C above spec.
Compliance-Informationen
RoHS compliant per ADI product page. Industrial-grade operating temperature range -40 to +85 °C. AEC-Q100 not applicable (industrial ADC, not automotive qualified).
