DM74LS138N - 3-to-8 Line Decoder/Demultiplexer, LS-TTL, 16-PDIP | onsemi
Teilenummer: DM74LS138N ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $1.2 | $1,20 |
| 10 | $1.05 | $10,50 |
| 100 | $0.88 | $88,00 |
| 500 | $0.72 | $360,00 |
| 1.000 | $0.58 | $580,00 |
DM74LS138N Übersicht
A decoder/demultiplexer is a combinational logic IC that translates a binary address on its inputs into a single selected output line. In its canonical role, the '138' family member accepts 3 address bits and activates exactly one of 8 outputs, which is why it is commonly referred to as a 1-of-8 decoder. It belongs to the broader hierarchy: decoder/demultiplexer -> combinational logic -> logic IC -> digital IC -> integrated circuit -> semiconductor. Common synonyms include '3-line to 8-line decoder', 'binary-to-octal decoder', and '1-of-8 demultiplexer'. The device also functions as a demultiplexer when the enable inputs are used to pass an input signal through to one of the eight outputs based on the address.
Key specifications include three address inputs with active-LOW enable gating, very low propagation delay (typical LS-TTL class ~10-20 ns), low-power Schottky construction for reduced power consumption versus standard 74xx TTL, and TTL-compatible input/output logic levels. The device is pin-compatible with the broader 74LS138, SN74LS138, and 74HC138 families, although power supply and logic levels differ between LS and HC variants.
Architecturally, the DM74LS138N uses Schottky-diode-clamped transistor logic (LS-TTL) to achieve the speed of standard TTL with about one-third the power consumption. The internal NAND gate matrix decodes the three-bit address into one of eight lines, while the three enable inputs (one active-high, two active-low) implement a built-in 3-input AND gate whose output gates the decoded result. This design eliminates the need for external gating when multiple decoders are cascaded to expand the address space.
Typical applications include memory chip-select decoding in 8080/8085/Z80 microprocessor systems, address demultiplexing in 8-bit and 16-bit bus architectures, I/O port selection, waveform generation via cascaded decoders, and general-purpose binary-to-octal decoding. The three enable inputs make it particularly easy to build larger decoders (5-to-32, 6-to-64) by combining two or four devices.
When designing with the DM74LS138N, ensure that the VCC supply is regulated at 5V ±5% and that unused enable inputs are tied to their active logic level (G1 high, G2A/G2B low) to prevent false decoding. Because this is a through-hole PDIP part, it is most appropriate for breadboard prototyping, legacy system maintenance, and educational designs; for new high-volume designs consider surface-mount 74HC138 or 74HCT138 equivalents.
This page synthesizes distributor pricing, verified drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in-Alternativen für DM74LS138N – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
SN74LS138N
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SN74HC138N
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SN74HCT138N
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
74LS138N
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
HD74LS138P
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
DM74LS138N Grenzwerte & elektrische Eigenschaften
| Funktion | 3-to-8 Line Decoder/Demultiplexer |
| Technology Family | LS-TTL (Low-power Schottky TTL) |
| Logic Configuration | 1 x 3:8 decoder/demux |
| Number of Address Inputs | 3 (A, B, C) |
| Anzahl der Ausgänge | 8 active-LOW (Y0-Y7) |
| Enable Inputs | 3 (G1 active-high, G2A and G2B active-low) |
| Output Polarity | Active LOW (mutually exclusive) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Input Logic Levels | TTL-compatible |
| Output Drive | LS-TTL standard |
| Betriebstemperatur | 0 C to +70 C (commercial) |
| Gehäuse | 16-pin PDIP (N16E), 0.300 inch wide, JEDEC MS-001 |
| Montageart | Through-Hole (DIP) |
| Pin-Anzahl | 16 |
| Moisture Sensitivity Level | 1 (unlimited floor life) |
DM74LS138N Pin-Konfiguration
| Pin 1 | A — Address input (LSB) |
| Pin 2 | B — Address input |
| Pin 3 | C — Address input (MSB) |
| Pin 4 | /G2A — Enable input, active LOW |
| Pin 5 | /G2B — Enable input, active LOW |
| Pin 6 | G1 — Enable input, active HIGH |
| Pin 7 | /Y7 — Output 7, active LOW |
| Pin 8 | GND — Ground |
| Pin 9 | /Y6 — Output 6, active LOW |
| Pin 10 | /Y5 — Output 5, active LOW |
| Pin 11 | /Y4 — Output 4, active LOW |
| Pin 12 | /Y3 — Output 3, active LOW |
| Pin 13 | /Y2 — Output 2, active LOW |
| Pin 14 | /Y1 — Output 1, active LOW |
| Pin 15 | /Y0 — Output 0, active LOW |
| Pin 16 | VCC — 5 V supply |
Typische Anwendungen
DM74LS138N ist geeignet für 6 Anwendungs: Memory Chip-Select Decoding in 8-bit Microprocessor Systems, Address Demultiplexing in 16-bit Bus Architectures, I/O Port Selection and Peripheral Address Mapping, Waveform and Pattern Generation via Cascaded Decoders, Binary-to-Octal Indicator Decoding for Front Panels, Legacy Industrial Control and Test Equipment Maintenance.
Memory Chip-Select Decoding in 8-bit Microprocessor Systems
The DM74LS138N is the canonical decoder for chip-select generation in 8080/8085/Z80/6502-style systems. With three address inputs A, B, C driven from the low-order address bus bits and G1 tied to a high-order address line, the decoder activates exactly one of eight memory or peripheral chips. The active-LOW outputs (/Y0-/Y7) directly drive 74LS-series chip-select pins, eliminating external gating logic. Compared to discrete diode decoding or PAL/GAL solutions, the DM74LS138N delivers sub-20 ns propagation delay, full TTL drive strength, and pin-selectable enables that allow two devices to form a 4-to-16 decoder with no extra glue logic.
Empfohlen
Address Demultiplexing in 16-bit Bus Architectures
In 16-bit systems such as the 8086 or 68000, the DM74LS138N is paired with a second '138 to demultiplex high-order address bits into individual device selects. The three enable inputs (G1 active-high, /G2A and /G2B active-low) implement a built-in 3-input AND gate, so a master DM74LS138N can decode the upper address bits while its outputs gate four slave decoders for a 5-to-32 or 6-to-64 address space. This cascading avoids the propagation-delay penalty and PCB complexity of diode-AND or discrete gate networks, while keeping the entire decoding tree in a single logic family.
Empfohlen
I/O Port Selection and Peripheral Address Mapping
Embedded designs use the DM74LS138N to map peripheral registers into a memory-mapped or I/O-mapped address space. By driving the address inputs from low-order bus lines and gating with a higher-order address line through G1, the decoder generates unique active-LOW strobes for UARTs, timers, parallel I/O chips, and analog converters. The 5 V TTL logic levels and 16 mA LS-TTL drive capability mean the DM74LS138N outputs can directly interface with most 5 V peripherals without buffering. Compared to CPLD-based address decoding, the DM74LS138N offers zero programming, instant availability, and immunity to firmware bitstream issues.
Empfohlen
Waveform and Pattern Generation via Cascaded Decoders
Two or more DM74LS138N devices can be cascaded through their enable inputs to generate timed sequences of output pulses for test equipment, stepper motor drivers, or LED multiplex displays. A master decoder clocks through outputs while feeding a slave decoder's /G2A enable, producing a 4-of-16 or 8-of-64 time-multiplexed pattern. The low LS-TTL propagation delay (~10-20 ns class) means the pattern can advance at frequencies well above audio range. Compared to dedicated sequencer ASICs, this DM74LS138N-based approach uses only standard logic and works at any 5 V CMOS clock rate.
Empfohlen
Binary-to-Octal Indicator Decoding for Front Panels
In industrial front panels and educational trainers, the DM74LS138N drives eight LEDs or seven-segment displays by decoding a 3-bit binary input. Each /Y0-/Y7 output sinks LED current directly through a series resistor, lighting the active position. Because outputs are mutually exclusive, no software multiplexing is required. Compared to a microcontroller-driven LED array, the DM74LS138N gives instant response with zero code overhead and survives in environments where firmware corruption is a risk.
Empfohlen
Legacy Industrial Control and Test Equipment Maintenance
Long-life industrial controllers and rack-mounted test instruments built in the 1980s and 1990s often contain DM74LS138N or its SN74LS138N sibling on backplane decoder cards. Because these systems run continuously for decades, the DM74LS138N remains in active production as a maintenance spare. Its 16-pin PDIP through-hole package is preferred for field-replaceable logic that technicians can swap without surface-mount rework. Compared to modern programmable logic, the DM74LS138N is universally understood, requires no programming equipment, and is sourced from multiple authorized distributors.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für DM74LS138N – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | SN74LS138N | SN74HC138N | SN74HCT138N | HD74LS138P |
|---|---|---|---|---|---|
| Brand | onsemi | Texas Instruments | Texas Instruments | Texas Instruments | Renesas Electronics |
| Package | 16-PDIP | 16-PDIP - same | 16-PDIP - same | 16-PDIP - same | 16-PDIP - same |
| Logic Family | LS-TTL | LS-TTL | CMOS (HC) | CMOS (HCT, TTL-input) | LS-TTL |
| VCC Range | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 2 V to 6 V | 4.5 V to 5.5 V | 4.75 V to 5.25 V |
| Inputs | 3 (A, B, C) TTL | 3 TTL | 3 CMOS | 3 TTL-compatible CMOS | 3 TTL |
| Outputs | 8 active-LOW | 8 active-LOW | 8 active-LOW | 8 active-LOW | 8 active-LOW |
| Enable Inputs | 3 (G1, /G2A, /G2B) | 3 | 3 | 3 | 3 |
| Operating Temperature | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C | -40 C to +85 C | -20 C to +75 C |
Wichtigste Unterscheidungsmerkmale
- Direct onsemi LS-TTL source with multi-decade production history (vs. SN74LS138N)
- Through-hole PDIP-16 format for legacy and prototyping systems (vs. SN74HC138DR)
- Built-in three-input enable for clean cascading (vs. 74LS139)
Designhinweise
The DM74LS138N is specified for 4.75 V to 5.25 V operation; absolute maximum VCC is 7 V per LS-TTL standards. Place a 0.1 uF ceramic decoupling capacitor as close as possible between pin 16 (VCC) and pin 8 (GND), and add a bulk 10 uF electrolytic on the supply rail feeding multiple '138 devices. Estimated: at 5 V and with all eight outputs switching at moderate CMOS loads, a single DM74LS138N consumes roughly 10-15 mA of quiescent plus dynamic current.
Always tie the three enable inputs (G1 high, /G2A low, /G2B low) to their active levels before applying address inputs; otherwise all outputs remain HIGH and the decoder appears 'stuck off'. For cascading, remember that /Y0-/Y7 are active-LOW, so the selected output goes LOW and the rest stay HIGH - downstream logic must accept active-LOW selects. Do not connect DM74LS138N outputs directly to 3.3 V CMOS logic without a level shifter; LS-TTL HIGH output of ~2.7 V may not exceed the 3.3 V CMOS VIH threshold.
For through-hole PDIP-16 designs, route address inputs (A, B, C) and the three enable lines (G1, /G2A, /G2B) on inner signal layers to minimize crosstalk on the long pin-to-trace paths. Place a 0.1 uF bypass within 5 mm of the VCC pin, and keep the ground return path short by using a continuous ground plane on the opposite board layer. Estimated: propagation delay through the '138 internal NAND matrix is on the order of 10-20 ns, so for synchronous designs budget at least one full LS-TTL delay for the decoder output plus one LS-TTL delay for downstream logic.
Because all eight outputs switch simultaneously when an address changes, the DM74LS138N draws a brief but significant current spike from VCC. Keep the VCC trace wide (at least 0.5 mm for 1 oz copper) and use generous local decoupling to prevent the spike from coupling into adjacent analog or reference circuitry. Estimated: at 5 V VCC with all outputs switching in 5 ns, peak instantaneous current can momentarily reach 50-80 mA per device.
Compliance-Informationen
RoHS, REACH, lead-free and halogen-free status not explicitly stated in the verified web data; refer to the onsemi DM74LS138 product page for current compliance certifications. AEC-Q100 not applicable for this commercial-grade PDIP logic IC.
