DS90UR124QVS - 24-Bit FPD-Link II Deserializer | Texas Instruments
Teilenummer: DS90UR124QVS ✓ AktivDS90UR124QVS Übersicht
An FPD-Link II interface is a serializer and deserializer technology used to transfer video data, control signals, and clock information over low-voltage differential signaling pairs. The DS90UR124 receives one serial FPD-Link II input and reconstructs 24 parallel outputs, providing a transparent link between a graphics source and a display receiver. Embedded clock forwarding removes the need for a separate source-synchronous clock trace, reducing the number of interconnects required for a wide parallel display bus.
The interface supports DC-balanced 24-bit transfers, including pixel data and associated synchronization or control channels. Its 5 MHz to 43 MHz clock range covers display timing requirements commonly encountered in industrial panels, automotive graphics systems, and embedded human-machine-interface displays. A maximum serial rate of 1.03 Gbps provides ample link headroom for the supported pixel-clock interval.
The DS90UR124 is the receiving half of the DS90UR241/124 chipset. The companion serializer converts a 24-bit parallel bus into a fully transparent FPD-Link II LVDS stream with embedded clock information. TI identifies this chipset as suitable for graphical data transport to displays requiring 18-bit color depth using RGB666 plus horizontal sync, vertical sync, data enable, and three additional general-purpose data channels.
The 64-pin TQFP package provides the required LVDS input, parallel data outputs, supply rails, reference network, and control connections. Because the package is not a thermally exposed package, board-level copper and airflow remain important when the deserializer operates near its full data rate in a high-temperature enclosure. Automotive-qualified ordering information identifies an operating range of -40°C to 105°C for the Q1 variant.
When integrating the DS90UR124, preserve the LVDS pair routing recommended in the manufacturer datasheet, keep the input pair geometry symmetrical, and place the required network and bypass components close to their associated pins. The deserializer also requires a stable reference for correct lane detection and data reconstruction, making reference-network layout as important as the high-speed differential routing.
This page summarizes the interface architecture, ordering options, application roles, and design considerations that help engineers evaluate the DS90UR124QVS before integrating it into an LVDS display link.
Drop-in-Alternativen für DS90UR124QVS – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
DS90UR124QVS/NOPB
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
DS90UR124QVSX/NOPB
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
DS90UR124IVS/NOPB
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
DS90UR124QVS Technische Daten
| Device Type | FPD-Link II Deserializer |
| Data Interface | FPD-Link II / LVDS |
| Parallel Output Width | 24 bits |
| Serial Input Count | 1 input |
| Parallel Output Count | 24 outputs |
| Pixel Clock Frequency Range | 5 MHz to 43 MHz |
| Maximum Data Rate | 1.03 Gbps |
| Encoding | DC-balanced 24-bit FPD-Link II |
| Clocking Method | Embedded clock forwarding |
| Ausgangstyp | LVCMOS |
| Input Type | FPD-Link II, LVDS |
| Supply Voltage Range | 3 V to 3.6 V |
| Package Type | 64-TQFP (PAG), 10 mm x 10 mm |
| Package Pin Count | 64 pins |
| Package Pitch | 0.50 mm |
| Package Height | 1 mm |
| Automotive Operating Temperature | -40°C to 105°C |
| Montageart | Surface Mount |
| Shipping Container Quantity | 160 units per tray |
| Automotive Qualification | AEC-Q100 grade option available as DS90UR124QVS/NOPB |
DS90UR124QVS 1 mm Pinbelegungsleitfaden
Pinbelegung für DS90UR124QVS (1 mm-Gehäuse). Pin-Nummerierung, Funktionen und Anschlussdiagramme sind im Herstellerdatenblatt definiert. Entnehmen Sie diesem den genauen Footprint und Lötrichtlinien.
Keine detaillierten Pinbelegungsdaten verfügbar für DS90UR124QVS.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
DS90UR124QVS ist geeignet für 6 Anwendungs: Industrial TFT Display Interfaces, Automotive Graphic Display Modules, Human-Machine Interface Panels, Medical Control Displays, Instrument and Test Equipment Displays, Embedded Control-System Screens.
Industrial TFT Display Interfaces
The DS90UR124QVS fits industrial TFT display links that need a compact cable-friendly connection between a graphics controller and a remote panel. Its 24 parallel LVCMOS outputs reconstruct a 24-bit FPD-Link II stream, while the supported 5 MHz to 43 MHz pixel-clock range covers many embedded display timing requirements. Embedded clock forwarding reduces the number of traces crossing between the controller and display, which is particularly useful when the panel is mounted behind a bezel or across a cable assembly. The 3 V to 3.6 V supply range suits compact embedded systems, and the 10 mm by 10 mm TQFP package allows routing on multilayer boards without the size of a large connector interface.
Empfohlen
Automotive Graphic Display Modules
The DS90UR124QVS is suitable for automotive graphic modules when the automotive-qualified ordering option is used. TI lists DS90UR124QVS/NOPB with a -40°C to 105°C operating range in a 64-pin TQFP package. The deserializer converts one FPD-Link II LVDS input into 24 parallel outputs, allowing a central vehicle graphics processor to drive a remote display over a compact differential link. A 1.03 Gbps maximum rate and 5 MHz to 43 MHz clock range support display data transfer while embedded clock forwarding eliminates a separate clock path. Automotive designs should also verify transient immunity, supplier traceability, and exact qualification requirements against the manufacturer documentation.
Empfohlen
Human-Machine Interface Panels
A DS90UR124-based link works well in human-machine-interface panels where pixel data must travel from a controller board to a separate touch or display module. Twenty-four parallel outputs cover 18-bit RGB data plus synchronization, data-enable, and general-purpose control channels described for the DS90UR241/124 chipset. The serial LVDS path simplifies routing across a hinged mechanism or internal cable compared with a wide parallel bus. The 5 MHz to 43 MHz range accommodates many standard embedded panel timings, while the DC-balanced transfer and embedded clock maintain a deterministic recovery path. Designers should follow the manufacturer layout guidance for the differential input, reference network, and supply bypassing.
Empfohlen
Medical Control Displays
The DS90UR124QVS can be used in a medical control system when a display module is separated from the main electronics by a differential FPD-Link II connection. Its 24 reconstructed outputs provide a broad parallel data path for RGB and control information, and the 1.03 Gbps link rate supplies throughput above the supported 5 MHz to 43 MHz pixel-clock range. Embedding the clock in the serial stream reduces the number of inter-board connections and removes a separate source-synchronous clock trace. For medical equipment, the complete system still requires the appropriate application-specific risk controls, while the interface device itself should be evaluated against its specified operating limits and quality documentation.
Empfohlen
Instrument and Test Equipment Displays
Test and measurement instruments often place a display behind a panel assembly where a wide parallel bus would be difficult to route. The DS90UR124QVS provides a compact LVDS input and 24 LVCMOS outputs, allowing a single FPD-Link II link to carry pixel data, synchronization, and control information. Its DC-balanced encoding supports reliable recovery across the internal board-to-panel connection, while embedded clock forwarding avoids carrying a separate clock. The 64-pin TQFP package provides enough routing density for reference and bypass components, but the lack of an exposed pad makes careful thermal layout important in sealed instruments. Use the manufacturer reference-network values and placement guidance rather than substituting generic capacitors.
Empfohlen
Embedded Control-System Screens
The DS90UR124QVS fits embedded control systems that transmit a wide video bus from a processor or programmable logic device to a local screen. The DS90UR241 companion serializer converts 24 parallel bits into the DC-balanced FPD-Link II stream, while the DS90UR124 reconstructs 24 outputs at the display end. The 5 MHz to 43 MHz range covers many embedded screen resolutions and refresh rates, and the maximum 1.03 Gbps rate provides additional channel margin. Because the TQFP package requires exact 0.50 mm pitch routing, PCB libraries and assembly drawings should be checked against the 10 mm by 10 mm package drawing before release.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für DS90UR124QVS – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | DS90UR124QVS/NOPB | DS90UR124QVSX/NOPB | DS90UR124IVS/NOPB |
|---|---|---|---|---|
| Package | 64-TQFP (PAG), 10 mm x 10 mm | 64-TQFP (PAG), 10 mm x 10 mm | 64-TQFP (PAG), 10 mm x 10 mm | 64-TQFP (PAG), 10 mm x 10 mm |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Function | 24-bit FPD-Link II deserializer | 24-bit FPD-Link II deserializer | 24-bit FPD-Link II deserializer | 24-bit FPD-Link II deserializer |
| Supported Pixel Clock | 5 MHz to 43 MHz | 5 MHz to 43 MHz | 5 MHz to 43 MHz | 5 MHz to 43 MHz |
| Maximum Data Rate | 1.03 Gbps | 1.03 Gbps | 1.03 Gbps | 1.03 Gbps |
| Parallel Output Width | 24 bits | 24 bits | 24 bits | 24 bits |
Wichtigste Unterscheidungsmerkmale
- Wide parallel display reconstruction in a single deserializer (vs. DS90UR124QVS/NOPB)
- Automotive-qualified ordering path with the same package and link performance (vs. DS90UR124QVS/NOPB)
- Compact 10 mm by 10 mm 64-pin TQFP footprint (vs. DS90UR124QVSX/NOPB)
Designhinweise
Route the FPD-Link II differential input as a tightly coupled pair with symmetric geometry and continuous reference where the manufacturer layout guidance calls for it. Keep the receiver and reference-network components close to their associated pins, and avoid forcing the pair through test pads, connectors, or layers with discontinuities that were not evaluated in the manufacturer reference layout. The embedded-clock architecture simplifies the connection, but it does not remove the need for controlled differential impedance.
Use the manufacturer pin-description table and 64-pin TQFP package drawing to create or verify the PCB footprint. The package is 10 mm by 10 mm with a 0.50 mm pitch, so pad and courtyard definitions should be checked against that geometry rather than estimated from a generic 64-pin library. Place the required supply bypass capacitors and reference components according to the datasheet layout to minimize parasitic effects on link recovery.
Estimated: package dissipation equals supply current multiplied by supply voltage, less useful output power; for example, 60 mA at 3.3 V corresponds to 198 mW before accounting for external load power. Because the 64-pin TQFP does not provide a dedicated exposed thermal pad, spread heat through the recommended PCB copper area and avoid enclosing the assembly without airflow. Use the manufacturer current limits and thermal information for final worst-case calculations.
Compliance-Informationen
The NOPB ordering option is identified as the lead-free, non-PB-free automotive-grade part. RoHS, REACH, halogen-free, and conflict-minerals declarations require confirmation against the specific manufacturer orderable part.
