ISL26312FVZ-T - 12-bit 125kSPS SAR ADC, 2-ch Diff | Renesas
Teilenummer: ISL26312FVZ-T ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $1.85 | $1,85 |
| 10 | $1.62 | $16,20 |
| 100 | $1.41 | $141,00 |
| 500 | $1.18 | $590,00 |
| 1.000 | $1.02 | $1.020,00 |
ISL26312FVZ-T Übersicht
A SAR ADC is a converter architecture that performs a binary search through an internal capacitive charge-redistribution DAC, evaluating one bit per conversion clock and producing the result on a single clock cycle without requiring a pipeline delay. SAR ADCs are prized for low-latency triggering, deterministic behavior on multiplexed inputs, and excellent DC linearity with no missing codes - and they remain the dominant choice for multi-channel precision industrial front-ends where both sample-accurate acquisition and lowest idle power matter.
Key specifications of this part include 12-bit resolution, 125 kSPS maximum sampling rate, ±10 V input range when configured for bipolar operation, true-differential analog inputs, an SPI-compatible serial interface, single 2.7 V to 5.25 V supply operation, and automotive-grade -40 °C to +125 °C temperature support. The 0.7 LSB typical DNL, on-chip track-and-hold, and integrated input multiplexer enable direct sensor interfacing with minimal external signal conditioning.
The on-chip sequencer and auto power-down state machine, combined with a flexible analog input mux, make the ISL26312FVZ-T straightforward to drop into multiplexed sensor panels, isolated transducer front-ends, and process-control loops. The SPI port operates in mode 0 and mode 3 and is easily framed by most FPGAs, microcontrollers, and digital isolators, so a single part can serve both 3.3 V MCU rails and 5 V legacy PLC backplanes.
Typical uses include industrial process instrumentation, multi-channel data loggers, motor-control feedback, isolated sensor readouts, and precision weigh-scale / strain-gauge signal chains. The wide 2.7 V to 5.25 V supply range tolerates either a regulated 3.3 V rail or a 5 V USB- or PLC-derived supply. Across all of these uses, the TSSOP-16 footprint keeps the converter area cost low and routing simple.
When designing with this device, place a 100 nF decoupling capacitor within 5 mm of the AVDD pin and a 10 µF bulk capacitor on the analog supply, route the analog and digital grounds through a star tie at the AGND pin, and verify SPI mode (CPOL/CPHA) against the host controller. For low-distortion input buffers, an op-amp rail-to-output driver such as the OPA2188 is recommended to avoid degrading the converter's DNL.
This page combines distributor pricing, pin-compatible drop-in alternatives, and application design notes into a single reference - saving engineering time versus cross-checking three separate component databases.
Drop-in-Alternativen für ISL26312FVZ-T – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit ISL26312FVZ-T (gleiche Bauform und Footprint) – abweichend in Number of Input Channels, Package, Input Type, Interface, Digital Supply Voltage (DVDD).
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
ISL26311FBZ
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$2.3 / Stück
Datenblatt ansehen →ISL26313FVZ
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
ISL26314FVZ
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$3.55 / Stück
Datenblatt ansehen →ISL26310FVZ
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
ISL26312FVZ-T7A
✅ Drop-In✓ Auf Lager
$3.55 / Stück
Datenblatt ansehen →ISL26312FVZ-T Grenzwerte & elektrische Eigenschaften
| Auflösung | 12 bits |
| Abtastrate | 125 kSPS |
| Number of Input Channels | 2 differential |
| Converter Architecture | SAR (Successive Approximation Register) |
| Input Configuration | Single-ended or differential |
| Supply Voltage (Single) | 2.7 V to 5.25 V |
| Power Consumption | 11 mW at 125 kSPS |
| Standby / Power-down Current | 8 µA typical (auto power-down between conversions) |
| Differential Non-Linearity (DNL) | 0.7 LSB typical |
| Digital Interface | SPI-compatible serial |
| Betriebstemperaturbereich | -40 °C to +125 °C |
| Gehäuse | TSSOP-16 |
| Montageart | Surface Mount |
| RoHS-Status | Compliant |
| Family / Series | ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319 |
ISL26312FVZ-T Pin-Konfiguration
| Pin 1 | AIN0+ — Positive analog input channel 0 (differential) |
| Pin 2 | AIN0- — Negative analog input channel 0 (differential) |
| Pin 3 | AIN1+ — Positive analog input channel 1 (differential) |
| Pin 4 | AIN1- — Negative analog input channel 1 (differential) |
| Pin 5 | AGND — Analog ground |
| Pin 6 | AVDD — Analog supply voltage (2.7 V to 5.25 V) |
| Pin 7 | REFIN — External reference voltage input |
| Pin 8 | REFOUT — Internal reference output (decoupling cap to AGND) |
| Pin 9 | DGND — Digital ground |
| Pin 10 | DVDD — Digital supply voltage (typically same as AVDD) |
| Pin 11 | /CS — Chip select (active low) for SPI interface |
| Pin 12 | SCLK — Serial clock for SPI interface |
| Pin 13 | SDI — Serial data input (MOSI) for SPI interface |
| Pin 14 | SDO — Serial data output (MISO) for SPI interface |
| Pin 15 | DRDY — Data ready output (active low) |
| Pin 16 | CONVST — Conversion start input |
Typische Anwendungen
ISL26312FVZ-T ist geeignet für 7 Anwendungs: Industrial Process Instrumentation, Multi-Channel Data Loggers, Precision Weigh-Scale and Strain-Gauge Front-Ends, Motor-Control Feedback Paths, Isolated Sensor Readout Modules, Battery-Aware IoT Sensor Nodes, PLC Analog Input Modules.
Industrial Process Instrumentation
The ISL26312FVZ-T fits industrial process instrumentation because its true-differential input pair, 12-bit/125 kSPS sampling, and 0.7 LSB DNL let it digitize bridge-type sensors (load cells, pressure transducers, strain gauges) directly without external amplification. Placed behind an instrumentation amp and a 4- to 20-mA loop barrier, the 2.7 V to 5.25 V single-supply operation lets the same PCB handle 3.3 V or 5 V PLC backplanes. Auto power-down between conversions (8 µA typical) keeps heat low inside sealed field enclosures.
Empfohlen
Multi-Channel Data Loggers
The ISL26312FVZ-T is well suited to multi-channel data loggers thanks to its on-chip analog multiplexer with two differential inputs and its low 11 mW power budget at full throughput. Cycled through channels at 125 kSPS aggregate rate and then placed into auto power-down between sweeps, it allows battery-powered loggers to record temperature, pressure, and voltage trends across days. The SPI-compatible port accepts framing from low-power Cortex-M0 MCUs and from FPGAs that buffer logs to SD cards.
Empfohlen
Precision Weigh-Scale and Strain-Gauge Front-Ends
The ISL26312FVZ-T suits precision weigh-scale front-ends because its 12-bit resolution and differential inputs digitize a full-bridge load cell signal directly, while 0.7 LSB DNL preserves linearity across the weighing range. Combined with a low-noise reference (e.g., REF5040) and an instrumentation amp, the 125 kSPS throughput supports fast settling for in-motion scales. Operating current is held to 8 µA between conversions, supporting battery-backed retail scales.
Empfohlen
Motor-Control Feedback Paths
The ISL26312FVZ-T fits motor-control feedback paths because its 125 kSPS sample rate and sub-microsecond SPI latency match the inner-current loop bandwidth of FOC-controlled BLDC and PMSM drives. The two differential channels digitize phase current via shunt resistors plus a DC-bus voltage signal in a single converter, eliminating two ADCs from the BOM. The -40 °C to +125 °C operating range survives under-the-hood and industrial inverter temperatures.
Empfohlen
Isolated Sensor Readout Modules
The ISL26312FVZ-T works well in isolated sensor readout modules because its SPI interface is easily framed through a digital isolator (e.g., ISO7741), allowing safe barrier isolation for medical or high-voltage monitoring. The TSSOP-16 footprint stays compact next to an isolated DC-DC bias supply, and the 2.7 V to 5.25 V supply range accepts the post-isolator regulated rail. Auto power-down reduces heat inside dense isolation modules.
Empfohlen
Battery-Aware IoT Sensor Nodes
The ISL26312FVZ-T fits battery-aware IoT sensor nodes because its 8 µA auto-power-down current and 11 mW active power let it run from coin cells for months while occasionally waking to sample temperature, light, or voltage channels. The wide 2.7 V to 5.25 V supply range accommodates Li-ion chemistries down to depletion, and the SPI port interfaces directly with energy-efficient Cortex-M0+ MCUs. TSSOP-16 footprint suits ultra-compact sensor node PCBs.
Empfohlen
PLC Analog Input Modules
The ISL26312FVZ-T works in PLC analog input modules where 24 V field signals are attenuated to ±10 V, because the differential input pair accepts bipolar input ranges when configured for bipolar mode. One ADC handles two channels per module, keeping BOM cost low across 8/16/32-channel PLC racks. The -40 °C to +125 °C operating range survives industrial cabinet temperatures, and SPI framing isolates the ADC through digital isolators as needed.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für ISL26312FVZ-T – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | ISL26311FBZ | ISL26313FVZ | ISL26314FVZ | ISL26310FVZ | ISL26312FVZ-T7A |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | TSSOP-16 | TSSOP-16 - same | TSSOP-16 - same | TSSOP-16 - same | TSSOP-16 - same | TSSOP-16 - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 125 kSPS | 125 kSPS | 125 kSPS | 125 kSPS | 125 kSPS | 125 kSPS |
| Number of Channels | 2 differential | 1 differential (single channel) | 4 single-ended | 4 differential | 1 single-ended | 2 differential |
| Supply Voltage | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V |
| Power Consumption | 11 mW at 125 kSPS | 11 mW at 125 kSPS | 11 mW at 125 kSPS | 11 mW at 125 kSPS | 11 mW at 125 kSPS | 11 mW at 125 kSPS |
| Digital Interface | SPI (mode 0/3) | SPI (mode 0/3) | SPI (mode 0/3) | SPI (mode 0/3) | SPI (mode 0/3) | SPI (mode 0/3) |
| Operating Temperature | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C |
| Series / Family | ISL26312 (2-ch diff) | ISL26311 (1-ch diff) | ISL26313 (4-ch SE) | ISL26314 (4-ch diff) | ISL26310 (1-ch SE) | ISL26312 (reel) |
Wichtigste Unterscheidungsmerkmale
- True differential input pair versus most single-ended 12-bit ADCs (vs. ISL26313FVZ)
- Wide 2.7 V to 5.25 V single-supply range accepting both 3.3 V MCU rails and 5 V PLC backplanes (vs. ISL26311FBZ)
- Reel-pack variant -T7A available with 250-piece MOQ for SMT production (vs. ISL26312FVZ-T7A)
Designhinweise
Place a 100 nF X7R ceramic decoupling capacitor as close as possible to the AVDD pin (within 5 mm) and a 10 µF bulk capacitor on the analog supply rail. This ADC's 11 mW active power gives light thermal loading, but the LSB at 12 bits is only ~0.6 mV on a 2.5 V full-scale, so a quiet analog rail is essential to preserve DNL. Tie AVDD and DVDD to the same supply via a ferrite bead if the digital load is noisy.
Use a star-ground topology that ties AGND and DGND at the converter's AGND pin only, then route analog and digital grounds on separate planes that join at that single point. Keep the analog input traces short and matched (within 5 mm) for the differential pair to avoid common-mode errors. The TSSOP-16 thermal pad is not internally connected and should be soldered to AGND for mechanical strength if present.
Do not leave the REFIN pin floating: connect it to REFOUT (with a 10 µF decoupling cap) for the internal reference configuration, or to an external reference such as the REF5040 for higher accuracy. A frequent design mistake is wiring the analog input pair to single-ended signals when the converter is in differential mode - the unused complementary input must still be biased to mid-supply (e.g., AVDD/2) to prevent input saturation.
When using the SPI port, route SCLK, SDI, SDO, /CS, and DRDY together over a continuous ground reference and keep them away from noisy switching nodes such as DC-DC converters or motor drivers. Adding 33 Ω series resistors near the driver pins reduces ringing on long SPI traces to FPGAs. For sub-µs settling on multiplexed channels, allow at least 3 acquisition-clock cycles before initiating conversion to avoid cross-channel crosstalk.
Compliance-Informationen
RoHS and lead-free compliance confirmed by LCSC and JLCPCB part detail. AEC-Q100 qualification status not listed in distributor data; industrial-grade temperature grade -40 °C to +125 °C supported.
