NVT2002DP118 - 2-Bit Bidirectional Level Translator | NXP
Teilenummer: NVT2002DP118 ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $0.3513 | $0,35 |
| 10 | $0.34 | $3,40 |
| 100 | $0.32 | $32,00 |
| 500 | $0.3 | $150,00 |
| 1.000 | $0.28 | $280,00 |
NVT2002DP118 Übersicht
A voltage level translator, also called a logic level shifter, is a signal-integrity interface IC that converts digital signals between circuits operating at different supply voltages. Within the signal-conversion hierarchy, the level translator sits under interface ICs and logic ICs, bridging mismatched voltage domains such as a 1.8 V microcontroller GPIO bank talking to a 5 V legacy peripheral, without loss of signal integrity.
Key features include true bidirectional operation without a direction pin, support for both open-drain and push-pull applications, a 1.0 V low-side capability that supports the latest low-voltage cores, and an enable (EN) pin that places all outputs in the high-impedance state when the device is disabled, reducing system power. All channels share identical electrical characteristics, so channel-to-channel skew is minimal - important for multi-bit buses.
Technically, the NVT2002 uses a one-shot architecture built around a reference-driven pass gate: VREF(A) sets the low-voltage domain, VREF(B) sets the high-voltage domain, and the internal one-shot accelerates rising edges so propagation delay stays in the nanosecond range for push-pull use. Because the I/O structure behaves like an open-drain output with pull-up to the local reference, it also transparently supports I2C-style open-drain buses at voltages from 1.0 V to 5 V.
Typical applications include interfacing 1.8 V MCUs to 3.3 V or 5 V sensors, I2C/SMBus level shifting between mixed-voltage domains, translating UART and SPI control lines in industrial systems, and bridging legacy 5 V logic to modern low-voltage processors.
Design consideration: pull-up resistor sizing on open-drain buses directly sets rise time and bus speed; follow the datasheet recommendations to balance current draw against edge rate at your target data rate.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in-Alternativen für NVT2002DP118 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
NVT2002DP,125
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
NVT2002DP118 Grenzwerte & elektrische Eigenschaften
| Translator Type | Bidirectional voltage level translator |
| Number of Channels | 2-bit |
| A-Side Reference Voltage (VREF(A)) | 1.0 V to 3.6 V |
| B-Side Reference Voltage (VREF(B)) | 1.8 V to 5.5 V |
| Translation Range | 1.0 V to 5 V |
| Direction Pin Required | No |
| Application Types | Open-drain and push-pull |
| Enable-Pin | Yes (EN, high-impedance outputs when disabled) |
| Gehäuse | TSSOP-8 (SOT505) |
| Montageart | Surface Mount |
| Ordering Code Suffix | ,118 (tape and reel, standard packing) |
| Channel Matching | All channels same electrical characteristics, minimal deviation |
NVT2002DP118 Pin-Konfiguration
| Pin 1 | A1 — A-side data input/output, channel 1 |
| Pin 2 | A2 — A-side data input/output, channel 2 |
| Pin 3 | GND — Ground |
| Pin 4 | B2 — B-side data input/output, channel 2 |
| Pin 5 | B1 — B-side data input/output, channel 1 |
| Pin 6 | VREF(B) — B-side reference voltage, 1.8 V to 5.5 V |
| Pin 7 | EN — Enable input; high-impedance outputs when disabled |
| Pin 8 | VREF(A) — A-side reference voltage, 1.0 V to 3.6 V |
Typische Anwendungen
NVT2002DP118 ist geeignet für 6 Anwendungs: I2C / SMBus Level Shifting, Mixed-Voltage MCU to Sensor Interfaces, Legacy 5 V Logic Interfacing, UART and SPI Control Line Translation, Battery-Powered Portable Devices, Automotive Body and Comfort Electronics.
I2C / SMBus Level Shifting
The NVT2002DP118's two channels map naturally onto the I2C SDA and SCL lines, letting a 1.8 V controller talk to 3.3 V or 5 V peripherals. Its open-drain-compatible I/O structure means wire-AND bus behavior is preserved without direction control, and translation spans 1.0 V to 5 V per the NXP datasheet. Pull-up resistors to VREF(A) and VREF(B) set rise time, so size them for the target bus speed (100 kHz standard mode tolerates larger resistors than 400 kHz fast mode). Because the EN pin tri-states the outputs, the bus can be isolated during reset or power sequencing.
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Mixed-Voltage MCU to Sensor Interfaces
Modern MCUs with 1.8 V GPIO banks frequently need to drive 3.3 V sensors, EEPROMs, or framer modules. The NVT2002DP118 accepts a 1.0 V to 3.6 V VREF(A), one of the lowest low-side references in its class, so it directly interfaces sub-1.8 V processors while delivering a full 5 V logic swing on the B side. Its push-pull support keeps edge rates fast enough for SPI chip-select and UART lines. With only two channels, it is ideal for clock-plus-data links where a single small TSSOP-8 replaces discrete transistor level-shift stages that suffer from slower and asymmetric edges.
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Legacy 5 V Logic Interfacing
Industrial retrofits often mix legacy 5 V TTL/CMOS devices with modern low-voltage controllers. The NVT2002DP118's B-side reference tolerates up to 5.5 V, so it safely produces and receives 5 V logic while keeping the 1.8 V to 3.3 V side protected. Bidirectional operation without a direction pin simplifies replacement of old bidirectional buffer stages (for example, on two-wire control links) without firmware changes. Over-voltage tolerance on the reference pins means mixed systems survive rail sequencing order, an important robustness factor during hot-plug and brown-out events in factory environments.
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UART and SPI Control Line Translation
Point-to-point push-pull links such as UART TX/RX pairs or SPI chip-select lines are straightforward use cases for the NVT2002DP118. Each channel translates independently and bidirectionally, and the datasheet notes all channels have the same electrical characteristics with minimal deviation, giving matched propagation delay on paired lines. In push-pull mode the internal one-shot actively accelerates rising edges, so high baud-rate UART links keep their eye margin. Reserve the part for two-signal links; wider buses need multiple devices or a wider translator.
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Battery-Powered Portable Devices
Portable and wearable designs translate between a low-voltage core domain (1.0 V to 1.8 V) and peripheral rails (3.3 V) while every microamp counts. The NVT2002DP118's EN pin lets firmware disconnect the translator, placing outputs in high-impedance and cutting dynamic current during sleep states. The tiny TSSOP-8 footprint (about 3 x 3 mm body) fits dense layouts. The 1.0 V low-side capability keeps the translator usable even with next-generation sub-1 V core rails, future-proofing the design as process nodes scale.
Empfohlen
Automotive Body and Comfort Electronics
Automotive modules mix 5 V sensor references with 3.3 V or lower logic; the NVT2002DP118 bridges LIN-adjacent two-wire links, diagnostic open-drain buses, and mixed-voltage sensor interfaces. Its open-drain mode suits K-line-style and shared diagnostic lines, while push-pull mode handles clocked sensor data. Consult the NXP portfolio for the AEC-Q100-qualified variant when the application demands automotive qualification - verify qualification status per ordering code on nxp.com before design-in. The 5.5 V B-side absolute maximum margin handles load-dump-induced rail excursions on regulated 5 V domains.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für NVT2002DP118 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | NVT2002DP,125 |
|---|---|---|
| Package | TSSOP-8 (SOT505) | TSSOP-8 - same |
| Brand | NXP Semiconductors | NXP Semiconductors |
| Bits / Channels | 2-bit | 2-bit |
| VREF(A) Range | 1.0 V to 3.6 V | 1.0 V to 3.6 V |
| VREF(B) Range | 1.8 V to 5.5 V | 1.8 V to 5.5 V |
| Direction Pin Required | No | No |
| Enable Pin | Yes | Yes |
Wichtigste Unterscheidungsmerkmale
- True 1.0 V low-side reference capability (vs. NVT2002DP,125)
- No direction pin required (vs. Discrete BJT level shifter stages)
- EN pin for bus isolation (vs. Simple passive divider solutions)
Designhinweise
In open-drain mode, rise time is set entirely by the pull-up resistor and total bus capacitance (tau = R x C). For I2C fast mode (400 kHz) keep the bus capacitance under 400 pF and size pull-ups per the NVT2001_NVT2002 datasheet application section; too large a resistor slows edges and truncates the high period, while too small a resistor wastes current and can exceed sink current limits. For push-pull signaling, the internal one-shot accelerates rising edges, so layout parasitics matter less but keep traces short to limit reflections.
Decouple both VREF(A) and VREF(B) with 100 nF ceramic capacitors placed within a few millimeters of pins 8 and 6 respectively. Because the two references set independent voltage domains, supply sequencing between the rails is generally tolerated by the open-drain structure, but verify the datasheet power-up behavior if one rail may be absent while the other is live. Use the EN pin during sleep states to tri-state the bus and eliminate static drive current through the pull-ups.
Do not exceed 3.6 V on VREF(A) or 5.5 V on VREF(B) - the A side is not 5 V tolerant because VREF(A) defines the low-domain clamp. Engineers migrating from discrete BJT level shifters sometimes connect the A side to a 5 V rail by mistake; this is the single most common failure mode. Also confirm that both channels carry signals at the same domain pair - the two VREF pins are shared, so one device cannot shift between two different domain pairs simultaneously.
Compliance-Informationen
Compliance declarations were not present in the retrieved web data; verify RoHS/REACH status on the official NXP product page for the NVT2002DP,118 ordering code before production release.
