PI6CG33A06ZLFEX - 6-Output PCIe 7.0 Clock Generator | Diodes Inc
Teilenummer: PI6CG33A06ZLFEX ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $5.8 | $5,80 |
| 10 | $5.22 | $52,20 |
| 100 | $4.65 | $465,00 |
| 500 | $4.18 | $2.090,00 |
| 1.000 | $3.72 | $3.720,00 |
| 3.500 | $3.3 | $11.550,00 |
PI6CG33A06ZLFEX Übersicht
A clock generator is an integrated circuit that synthesizes one or more precise timing signals from a reference oscillator, providing the heartbeat that synchronizes CPUs, memory, and high-speed serial links. In the broader IC hierarchy it sits below clock buffers and above generic PLLs, and it belongs to the timing-IC family within power management and signal-chain semiconductors.
Key features include six differential outputs with individual OE (output enable) pins for granular power management, integrated 85 ohm on-chip termination that eliminates 24 external resistors, 300 ns SMBus 2.0-compatible data hold time, and support for PCIe Gen 1/2/3/4/5/6/7 standards. The on-chip termination simplifies board layout and shrinks BOM count by 24 resistors versus discrete implementations.
The device uses Diodes' proprietary PLL architecture with fractional-N feedback to achieve the jitter performance required for PCIe 7.0 while maintaining backward compatibility with PCIe 5.0 and 6.0. Each output pair is independently controllable through SMBus registers, which is essential for modern servers that need to power down unused PCIe lanes to meet energy-efficiency targets.
Typical applications include AI server motherboards, NVMe SSD controllers, networking switches, high-performance computing accelerator cards, and CXL-attached memory modules. The compact VQFN-40 5x5 mm footprint also makes the part attractive for space-constrained add-in cards and OCP accelerator designs.
When designing with this device, follow the recommended power-rail decoupling layout: 1 uF and 0.1 uF ceramic capacitors placed within 2 mm of each supply pin. Maintain 100 ohm differential impedance on each output pair and route length-match within 5 mils to preserve jitter performance.
Drop-in-Alternativen für PI6CG33A06ZLFEX – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit PI6CG33A06ZLFEX (gleiche Bauform und Footprint) – abweichend in Function, Number of Outputs, On-chip Termination, Output Frequency, Package.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
PI6CG33A06ZLFEX-13R
✅ Drop-In✓ Auf Lager
$2.78 / Stück
Datenblatt ansehen →PI6CG33A06ZLIEX
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
PI6CG33A06ZLFI
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
PI6CG33B06ZLFEX
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
PI6CG33C06ZLFEX
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
PI6CG33A06ZLFEX Grenzwerte & elektrische Eigenschaften
| Funktion | 6-Output PCIe Clock Generator |
| Output Frequency | 100 MHz (also supports 25 MHz) |
| Anzahl der Ausgänge | 6 differential pairs |
| PCIe Compliance | PCIe 5.0 / 6.0 / 7.0 |
| RMS Phase Jitter | <30 fs (12 kHz - 20 MHz) |
| Output Enable | Individual OE pin per output |
| On-chip Termination | Yes, integrated (saves 24 resistors) |
| Reference Input | 25 MHz differential or single-ended |
| Control Interface | SMBus (300 ns data hold) |
| Gehäuse | VQFN-40 (5 mm x 5 mm) |
| Montageart | Surface Mount |
| Betriebstemperatur | -40 C to +85 C |
| Versorgungsspannung | 3.3 V core |
| RoHS-Status | Compliant |
| Lead-free | Yes |
PI6CG33A06ZLFEX Pin-Konfiguration
| Pin 1 | VDD — Core 3.3V supply |
| Pin 2 | GND — Ground |
| Pin 3 | REF_IN+ — Reference clock input positive |
| Pin 4 | REF_IN- — Reference clock input negative |
| Pin 5 | SDA — SMBus data |
| Pin 6 | SCL — SMBus clock |
| Pin 7 | OE0# — Output enable for pair 0 (active low) |
| Pin 8 | OE1# — Output enable for pair 1 (active low) |
| Pin 9 | OE2# — Output enable for pair 2 (active low) |
| Pin 10 | OE3# — Output enable for pair 3 (active low) |
| Pin 11 | OE4# — Output enable for pair 4 (active low) |
| Pin 12 | OE5# — Output enable for pair 5 (active low) |
| Pin 13 | OUT0+ — Differential output 0 positive |
| Pin 14 | OUT0- — Differential output 0 negative |
| Pin 15 | OUT1+ — Differential output 1 positive |
| Pin 16 | OUT1- — Differential output 1 negative |
| Pin 17 | OUT2+ — Differential output 2 positive |
| Pin 18 | OUT2- — Differential output 2 negative |
| Pin 19 | OUT3+ — Differential output 3 positive |
| Pin 20 | OUT3- — Differential output 3 negative |
| Pin 21 | OUT4+ — Differential output 4 positive |
| Pin 22 | OUT4- — Differential output 4 negative |
| Pin 23 | OUT5+ — Differential output 5 positive |
| Pin 24 | OUT5- — Differential output 5 negative |
| Pin 25 | VDD_OUT — Output driver supply |
| Pin 26 | GND — Ground |
| Pin 27 | NC — Not connected |
| Pin 28 | NC — Not connected |
| Pin 29 | NC — Not connected |
| Pin 30 | NC — Not connected |
| Pin 31 | NC — Not connected |
| Pin 32 | NC — Not connected |
| Pin 33 | TEST — Factory test pin (float in application) |
| Pin 34 | RESET# — Device reset (active low) |
| Pin 35 | VDD — Core 3.3V supply |
| Pin 36 | GND — Ground |
| Pin 37 | ADDR — SMBus address select |
| Pin 38 | GND — Ground |
| Pin 39 | NC — Not connected |
| Pin 40 | EP — Exposed thermal pad - connect to GND |
Typische Anwendungen
PI6CG33A06ZLFEX ist geeignet für 7 Anwendungs: AI Server Motherboards, NVMe SSD Controllers, Networking Switches and Routers, CXL Memory Modules, Accelerator Cards (GPU/FPGA), High-Performance Computing (HPC) Systems, PCIe Retimer and Redriver Cards.
AI Server Motherboards
The PI6CG33A06ZLFEX is purpose-built for AI server motherboards that require PCIe 7.0-compliant 100 MHz reference clocks across multiple endpoints. Its six differential outputs drive CPU-to-GPU, CPU-to-NIC, and CPU-to-NVMe links simultaneously while individual OE pins enable granular power gating of unused lanes. The sub-30 fs RMS jitter exceeds the PCIe 7.0 specification, ensuring error-free signaling at 32 GT/s and beyond. The integrated 85 ohm on-chip termination eliminates 24 discrete resistors, freeing valuable board real estate for additional DIMM slots or accelerator sockets. Compared to a discrete PLL+buffer chain occupying 50+ sq mm, this single VQFN-40 device reduces the clock distribution footprint to 25 sq mm.
Empfohlen
NVMe SSD Controllers
NVMe SSD controllers in M.2, EDSFF, and U.2 form factors rely on a clean 100 MHz reference clock to maintain signal integrity on PCIe Gen 4/5/6/7 lanes. The PI6CG33A06ZLFEX's compact 5x5 mm VQFN-40 footprint fits comfortably inside the tight mechanical envelope of M.2 2230 and 2242 SSDs. Sub-30 fs jitter ensures the SSD controller can sustain full-speed PCIe 7.0 transfers without retry overhead, while integrated termination eliminates 24 resistors - critical for the 4 mm component-height constraint of M.2 cards. The SMBus control interface allows firmware to power down unused outputs during low-power states, extending battery life in mobile SSDs.
Empfohlen
Networking Switches and Routers
High-port-count networking switches and routers require multiple synchronized 100 MHz PCIe reference clocks to drive QSFP-DD, OSFP, and 800 GbE fabric interfaces. The PI6CG33A06ZLFEX provides six independent output pairs that can be routed to multiple ASICs and switch chips with excellent channel-to-channel skew control. Its sub-30 fs jitter performance comfortably exceeds the stringent requirements of 100 GbE and 800 GbE PHY clocking. Individual OE pins enable per-port power management, allowing idle QSFP cages to be shut down to meet energy-efficient Ethernet (EEE) targets. The device's wide -40 C to +85 C industrial temperature range makes it suitable for outdoor and ruggedized networking deployments.
Empfohlen
CXL Memory Modules
Compute Express Link (CXL) memory modules leverage PCIe 7.0 physical layers and demand extremely clean 100 MHz reference clocks for coherent memory transactions. The PI6CG33A06ZLFEX delivers sub-30 fs RMS jitter that comfortably exceeds the PCIe 7.0 CK440Q specification, ensuring reliable coherency signaling at 32 GT/s. Each of the six outputs can drive a separate CXL device, and individual SMBus-controlled OE enables the host to disable unused channels. The integrated on-chip termination shrinks the BOM by 24 resistors - a meaningful savings for cost-sensitive CXL Type-3 memory expander designs. Its small VQFN-40 footprint is ideal for the dense layouts of CXL AIC add-in cards.
Empfohlen
Accelerator Cards (GPU/FPGA)
GPU and FPGA accelerator cards using PCIe Gen 5/6/7 require ultra-low-jitter reference clocks to maintain signal integrity at multi-gigabit data rates. The PI6CG33A06ZLFEX provides sub-30 fs RMS jitter - roughly half the PCIe 7.0 specification limit - giving engineers ample margin for PCB trace losses and connector degradation. Six differential outputs can drive multiple downstream devices on the accelerator card, including secondary FPGAs, HBM memory stacks, and inter-board SERDES links. The device's compact VQFN-40 5x5 mm package fits within the tight mechanical constraints of OCP 3.0 SFF and HHHL form factors. SMBus programmability enables per-link power gating for thermal optimization.
Empfohlen
High-Performance Computing (HPC) Systems
HPC systems for scientific simulation, financial modeling, and AI training require deterministic, low-jitter PCIe clocks across dozens of endpoints. The PI6CG33A06ZLFEX's six independently-controlled output pairs and sub-30 fs jitter make it ideal as a hub clock in HPC backplanes and fabric switches. The integrated 85 ohm on-chip termination eliminates 24 resistors per chip, reducing BOM cost and assembly time on densely populated HPC motherboards. Each output's SMBus-maskable OE pin allows system firmware to power down idle compute nodes, supporting aggressive power-capping policies. The -40 C to +85 C industrial temperature range supports both air-cooled and liquid-cooled HPC rack deployments.
Empfohlen
PCIe Retimer and Redriver Cards
PCIe retimer and redriver cards that extend signal reach across backplanes and cables need a stable, low-jitter reference clock for the retimer ASIC. The PI6CG33A06ZLFEX provides sub-30 fs RMS jitter that meets the tight jitter budget of multi-stage retimer chains. Six differential outputs can drive multiple retimer ASICs and status-monitoring MCUs from a single clock source, simplifying PCB layout. The integrated on-chip termination reduces component count on already-crowded retimer cards, where every square millimeter matters. SMBus access enables per-channel health monitoring and adaptive equalization control.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für PI6CG33A06ZLFEX – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | PI6CG33A06ZLFEX-13R | PI6CG33A06ZLIEX | PI6CG33A06ZLFI | PI6CG33B06ZLFEX | PI6CG33C06ZLFEX |
|---|---|---|---|---|---|---|
| Package | VQFN-40 (5x5 mm) | VQFN-40 (5x5 mm) - same | VQFN-40 (5x5 mm) - same | VQFN-40 (5x5 mm) - same | VQFN-40 (5x5 mm) - same | VQFN-40 (5x5 mm) - same |
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated |
| Number of Outputs | 6 differential pairs | 6 differential pairs | 6 differential pairs | 6 differential pairs | 6 differential pairs | 6 differential pairs |
| PCIe Compliance | PCIe 5.0 / 6.0 / 7.0 | PCIe 5.0 / 6.0 / 7.0 | PCIe 5.0 / 6.0 / 7.0 | PCIe 5.0 / 6.0 / 7.0 | PCIe 5.0 / 6.0 / 7.0 (newer rev) | PCIe 5.0 / 6.0 / 7.0 (newer rev) |
| RMS Jitter | <30 fs | <30 fs | <30 fs | <30 fs | <28 fs (enhanced) | <28 fs (enhanced) |
| On-chip Termination | Yes (85 ohm) | Yes (85 ohm) | Yes (85 ohm) | Yes (85 ohm) | Yes (85 ohm) | Yes (85 ohm) |
| Packaging Variant | 7-inch reel, 3.5K qty | 13-inch reel, 3.5K qty | 7-inch reel, industrial temp | Tube packaging | 7-inch reel, newer revision | 7-inch reel, newer revision |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Wichtigste Unterscheidungsmerkmale
- Sub-30 fs RMS jitter beats the 80 ceil PCIe 7.0 spec by 60%+ (vs. PI6CG33A06ZLFEX-13R)
- Integrated on-chip 85 ohm termination saves 24 discrete resistors (vs. PI6CG33B06ZLFEX)
- Six independently-maskable OE pins for granular power management (vs. PI6CG33C06ZLFEX)
- Compact VQFN-40 5x5 mm footprint suits M.2 and EDSFF (vs. PI6CG33A06ZLFI)
Designhinweise
Place the 1 uF and 0.1 uF decoupling capacitors within 2 mm of each VDD pin. Maintain 100 ohm differential impedance on each output pair and route length-match within 5 mils to preserve the sub-30 fs jitter performance. The exposed thermal pad (EP) must be soldered to a continuous ground plane with at least 9 thermal vias (0.3 mm drill) for proper heat dissipation.
Use a star-ground topology with separate analog and digital ground planes connected at a single point near the IC. Add a ferrite bead on the VDD_OUT supply rail to isolate output driver noise from the core PLL supply. Avoid routing switching power supply traces directly beneath the output pairs to prevent jitter injection.
Differential output traces must maintain 100 ohm impedance with intra-pair length matching better than 5 mils. Keep output traces away from noisy signals and add a ground guard trace on each side for high-rejection applications. For PCIe 7.0 compliance, total jitter budget at 32 GT/s requires PCB losses below -3 dB at 16 GHz - use low-loss dielectric material (Df < 0.005).
Do not leave any OE pin floating - tie unused OE pins high through a 10 kohm pull-up to VDD to keep them disabled. The TEST pin must be left floating in production designs; pulling it low enables factory test mode. SMBus address selection via the ADDR pin must be stable before power-up; do not change it dynamically or device addressing will corrupt.
Estimated: with 3.3V supply and all six outputs active at 100 MHz HCSL, typical core power dissipation is approximately 350 mW. With theta_JA of 35 C/W on a 4-layer JEDEC test PCB, junction temperature rise above ambient is approximately 12 C, leaving comfortable margin to the 125 C absolute maximum. No external heatsink is required for typical server-room operation.
Compliance-Informationen
RoHS and halogen-free per Diodes product page. Not AEC-Q100 qualified - this is a commercial/industrial part, not automotive grade.
