PS8925 - 16Gbps PCIe Gen 4 4-Lane Retimer | Parade Technologies
Teilenummer: PS8925 ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $12.5 | $12,50 |
| 10 | $11.2 | $112,00 |
| 100 | $9.85 | $985,00 |
| 500 | $8.4 | $4.200,00 |
| 1.000 | $7.2 | $7.200,00 |
PS8925 Übersicht
A retimer is a mixed-signal device that sits between a PCIe root complex or endpoint and a downstream receiver. Unlike a simple redriver, a retimer contains a clock-data recovery (CDR) stage that fully re-samples the incoming bit stream before re-transmitting it, eliminating accumulated jitter and ISI rather than merely compensating for them. Within the broader PCIe hierarchy, retimers operate below the protocol layer and above the physical layer; in signal-conditioning taxonomy, they sit alongside redrivers, re-drivers, and repeaters. The PS8925 supports PCIe Gen 4 (16 GT/s) and is backward-compatible with Gen 3 (8 GT/s), Gen 2 (5 GT/s), and Gen 1 (2.5 GT/s) auto-negotiated link speeds.
Key features of the PS8925 include a per-lane configurable CTLE/DFE adaptive equalizer for receive-side compensation, a de-emphasis transmitter with multiple boost levels, integrated 100 MHz reference clock distribution, support for SMBus / I2C sideband configuration, and per-channel diagnostic eye-margin monitoring accessible through the management interface. The retimer also provides loss-of-signal and ready-status interrupts to the host. The bidirectional architecture lets a single device condition both upstream and downstream directions, simplifying PCB routing and BOM.
In terms of architecture, the PS8925 uses a CDR-based SerDes core per channel with on-die termination, supply-rail decoupling, and an internal PLL synchronized to the PCIe reference clock. Its adaptive engine continuously tunes CTLE and DFE tap weights to track channel variations caused by temperature drift, connector wear, and link-partner training. This makes the device particularly effective in systems that must pass strict PCIe Gen 4 compliance at the system level.
Typical applications for the PS8925 include enterprise server motherboards, NVMe SSD storage backplanes, workstation add-in cards, high-performance riser and backplane assemblies, and AI accelerator fabric expansion boards. It is especially valuable when the host CPU, GPU, or NVMe controller sits far from the physical PCIe slot and link-training fails without active signal recovery.
When designing with the PS8925, allocate a clean 0.9 V core rail and a 1.8 V PHY rail with low-impedance decoupling placed within 3 mm of each BGA power ball. Maintain 90 ohm differential impedance on all TX/RX pairs and minimize via stubs by using back-drilling on thicker backplanes. Always validate final eye margins at the slot connector with the retimer in place.
Drop-in-Alternativen für PS8925 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
PS8925BGA146GTR-A2
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PS8925BGA146GTR
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
DS160PT801
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PS8925 Technische Daten
| Funktion | PCI Express Gen 4 bidirectional retimer |
| Number of Lanes | 4 lanes (8 data channels, bidirectional) |
| PCIe Standard | PCIe Gen 4 (backward compatible with Gen 1/2/3) |
| Maximum Data Rate | 16 Gbps (GT/s) per lane |
| Direction | Bidirectional |
| Equalization | Adaptive CTLE + DFE on RX, de-emphasis on TX |
| Latency Profile | Low-latency |
| Configuration Interface | SMBus / I2C sideband |
| Reference Clock | 100 MHz PCIe reference clock |
| Gehäuse | BGA-146 (PS8925BGA146GTR-A2) |
| Target Applications | Workstations, enterprise servers, storage, data center |
| Compliance | PCI-SIG PCIe Gen 4 compliant |
| Diagnostic Features | Per-channel eye-margin monitoring |
| Status Indicators | Loss-of-signal and ready-status interrupts |
| Manufacturer | Parade Technologies, Ltd. |
| Orderable Part Number | PS8925BGA146GTR-A2 |
PS8925 bga-146 (ps8925bga146gtr-a2) Pinbelegungsleitfaden
Pinbelegung für PS8925 (bga-146 (ps8925bga146gtr-a2)-Gehäuse). Pin-Nummerierung, Funktionen und Anschlussdiagramme sind im Herstellerdatenblatt definiert. Entnehmen Sie diesem den genauen Footprint und Lötrichtlinien.
Keine detaillierten Pinbelegungsdaten verfügbar für PS8925.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
PS8925 ist geeignet für 6 Anwendungs: Enterprise Server Motherboards, NVMe SSD Storage Backplanes, Workstation Add-in Cards, AI Accelerator Fabric Expansion, Riser Card and Backplane Assemblies, High-Performance Computing (HPC) Nodes.
Enterprise Server Motherboards
The PS8925 retimes PCIe Gen 4 lanes between the host CPU/SoC and downstream PCIe slots on enterprise server motherboards. With 4 bidirectional lanes (8 channels) and adaptive CTLE/DFE equalization, it restores eye margins across long CPU-to-slot traces that exceed 12 inches of FR4, where Gen 4 at 16 Gbps would otherwise fail link training. The low-latency CDR preserves cache-coherent traffic performance, and the BGA-146 package fits standard server PCB layouts. Designers should pair the PS8925 with a clean 100 MHz PCIe reference clock and route all differential pairs at 85 ohm impedance.
Empfohlen
NVMe SSD Storage Backplanes
The PS8925 is well suited for NVMe SSD storage backplanes where many Gen 4 drives fan out from a single PCIe switch or RAID controller. Each retimer conditions 4 bidirectional lanes through a backplane connector, eliminating signal degradation caused by the connector transition and backplane stub. The integrated eye-margin monitor lets the BMC log link health per drive bay, and SMBus configuration supports per-bay equalization tuning. The PS8925's low-latency operation ensures that storage read/write latency remains predictable, which is critical for high-IOPS database workloads.
Empfohlen
Workstation Add-in Cards
The PS8925 enables workstation add-in cards such as GPU compute accelerators, capture cards, and DSP expansion boards to recover PCIe Gen 4 signals routed through long card-edge fingers and riser connectors. Its bidirectional 4-lane architecture matches typical x4 endpoint designs, while adaptive equalization handles the lossy edge-finger-to-host topology. The BGA-146 footprint fits standard x4 card real estate, and the SMBus interface allows the host BIOS to read the retimer's link-training diagnostics during POST.
Empfohlen
AI Accelerator Fabric Expansion
The PS8925 conditions PCIe Gen 4 links in AI training fabrics where multiple GPU or accelerator cards communicate through backplane midplanes. At 16 Gbps Gen 4, signal integrity across the midplane is critical to maintaining high effective bandwidth for gradient synchronization. The PS8925's adaptive CTLE/DFE continuously retunes to compensate for temperature drift across the rack, and the CDR-based architecture removes jitter that would otherwise propagate between accelerator nodes. Designers typically place one PS8925 per fabric channel pair.
Empfohlen
Riser Card and Backplane Assemblies
The PS8925 is ideal for riser card and backplane assemblies where PCIe Gen 4 signals must traverse one or more high-density connectors and long internal trace routes. The retimer's adaptive engine learns the channel response during link training and applies optimal CTLE/DFE tap weights, while the TX de-emphasis pre-compensates for the upcoming loss. This makes the PS8925 especially valuable in modular server chassis that mix Gen 4 and Gen 5 add-in cards. The SMBus interface exposes register access for in-field diagnostics across the backplane management plane.
Empfohlen
High-Performance Computing (HPC) Nodes
In HPC nodes, the PS8925 retimes PCIe Gen 4 interconnects between compute nodes, coherent fabrics, and accelerator pools. Its low-latency CDR preserves the tight timing budgets required for HPC message-passing workloads, while bidirectional 4-lane support matches typical node-to-node Gen 4 topologies. The BGA-146 package enables dense PCB layouts common to HPC sled designs. Eye-margin monitoring through SMBus provides a per-link health telemetry stream that HPC cluster managers can use to predict and preempt interconnect failures.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für PS8925 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | PS8925BGA146GTR-A2 | PS8925BGA146GTR | DS160PT801 |
|---|---|---|---|---|
| Package | BGA-146 | BGA-146 (same) | BGA-146 (same) | BGA-146 (compatible per TI E2E) |
| Brand | Parade Technologies | Parade Technologies | Parade Technologies | Texas Instruments |
| Function | PCIe Gen 4 retimer (4-lane) | Same retimer | Same retimer | PCIe Gen 4 redriver (8-ch) |
| Max Data Rate | 16 Gbps (PCIe Gen 4) | 16 Gbps | 16 Gbps | 16 Gbps |
| Lane Count | 4 bidirectional (8 channels) | 4 lanes | 4 lanes | 8 channels (redriver) |
| Equalization | Adaptive CTLE + DFE + TX de-emphasis | Same | Same | Linear equalizer (redriver) |
| Configuration Interface | SMBus / I2C | SMBus | SMBus | I2C / SMBus |
| Latency Profile | Low-latency | Low-latency | Low-latency | Low (redriver, analog path) |
Wichtigste Unterscheidungsmerkmale
- Bidirectional 4-lane retimer (CDR-based) vs redriver architectures (vs. TI DS160PT801 (redriver))
- Adaptive CTLE + DFE on RX plus de-emphasis on TX (vs. TI DS160PT801 (linear EQ only))
- Per-channel eye-margin diagnostics over SMBus (vs. TI DS160PT801)
Designhinweise
Estimated: Provide a clean 0.9 V core rail and 1.8 V PHY rail to the PS8925. Place low-ESR 10 uF bulk plus 0.1 uF and 1 nF decoupling within 3 mm of each BGA power ball. Use a wide power plane stitched with multiple vias to keep impedance below 1 mOhm at 100 MHz; noise on the 0.9 V rail directly degrades CDR jitter performance and can cause link-training retries.
Maintain 85 ohm differential impedance (90 ohm is acceptable per PCIe spec) with intra-pair skew below 5 mil and inter-pair length matching within 20 mil. Minimize via stubs by back-drilling any via used on TX/RX pairs on backplanes thicker than 2 mm. Route the 100 MHz PCIe reference clock with the same impedance and keep it isolated from switching power nets to avoid coupling into the CDR.
Always validate final eye margins at the slot connector with the PS8925 in place. The retimer's adaptive CTLE/DFE re-trains on every link-up, but the upstream redriver (if any) must be set such that the retimer's input does not saturate. Use the SMBus eye-margin registers to log compliance margin per channel during system bring-up, which provides a field diagnostic for production validation.
The BGA-146 package dissipates roughly 1-1.5 W under full Gen 4 traffic on all 8 channels. Provide a thermal pad array or copper pour directly under the BGA connected to the inner ground plane, with at least 8 thermal vias (0.3 mm drill) to spread heat. Estimate: at 1.2 W with theta_JA near 25 C/W on a 6-layer server PCB, junction rises about 30 C above ambient - keep ambient below 70 C for reliable operation.
Compliance-Informationen
PCI-SIG PCIe Gen 4 base specification compliance per Parade Technologies product page. RoHS/REACH/lead-free status not stated in verified web data; treat as unknown until confirmed from the official datasheet.
