Latencia en IA de borde: por qué el tiempo de evento a respuesta, y no la velocidad del modelo, define los diseños embebidos en tiempo real

Reported by Embedded on 2026-10-14. Summarized and analyzed by XAIPART Editorial.

What happened

Embedded.com argues that real-time edge AI is governed by end-to-end event-to-response latency, not by how quickly a neural network finishes a single forward pass. The outlet describes true latency as the time from sensor capture through inference to the actuator trigger, noting that a system averaging 5 ms per inference can still fail a real-time deadline when occasional spikes reach 30 to 40 ms.^S1

The article identifies DMA-driven double buffering as a standard technique for overlapping acquisition with computation, and flags pre-processing (scaling, filtering, normalization, FFT, feature extraction) as a stage that can exceed the inference cost itself on an MCU.^S1

On hardware selection, the piece walks from Cortex-M class MCUs for anomaly detection up to heterogeneous CPU plus GPU plus NPU platforms, citing Arm ethos-U NPUs working alongside Cortex-M cores as a concrete example of offloading matrix and tensor work from the CPU.^S1

On model optimization, the outlet covers INT8 quantization, input resolution reduction (mentioning 96 by 96-pixel images as a low-data option), pruning, and layer-count trimming, while warning that operators unsupported by the chosen accelerator force a CPU-NPU-CPU round trip and reintroduce latency. It also replaces isolated benchmarks with full-chain profiling under realistic temperature, CPU load, and traffic conditions, and illustrates a 20 ms time budget: 4 ms acquisition, 3 ms pre-processing, and 13 ms remaining for inference plus post-processing plus actuator signaling.^S1

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.