ADC/DAC
Productos (2518)
KAD2710C-27Q68 - 10-Bit 275MSPS ADC, 68-QFN | Renesas/Intersil
The Renesas (formerly Intersil) KAD2710C-27Q68 is a 10-bit, 275 MSPS, high-performance pipelined analog-to-digital converter housed in a 68-pin QFN (10x10 mm) package. It uses Intersil's proprietary FemtoCharge technology on a standard CMOS process to deliver 55.6 dBFS SNR at fIN = 138 MHz while consuming less than 265 mW from a 1.8 V analog supply. The -27 speed grade is the highest sample-rate option in the KAD2710C family. A pipelined ADC (Analog-to-Digital Converter) is a high-speed data converter that processes analog input signals by splitting conversion into successive low-resolution stages, each operating on a delayed sample of the input. Pipelined ADCs sit in the data-acquisition hierarchy as follows: ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor. They are the workhorse of high-speed IF sampling, communications receivers, and instrumentation. Key features of the KAD2710C-27Q68 include an over-range indicator, a selectable divide-by-2 input clock buffer, LVDS-compatible outputs for noise-immune digital signaling, and a wide analog input bandwidth that supports undersampling of IF signals. The 1.7 V to 1.9 V analog and digital supply rails and integrated reference simplify power-tree design, while the exposed paddle QFN-68 package keeps the junction-to-ambient thermal resistance low for sustained full-rate operation. FemtoCharge technology is a switched-capacitor architecture that reduces the input-referred noise and kT/C sampling error typical of CMOS ADCs, allowing the KAD2710C to combine 10-bit resolution with 275 MSPS sampling without an expensive SiGe or BiCMOS process. The 1.8 V LVDS outputs minimize EMI in dense digital fan-out paths and pair naturally with FPGA LVDS receivers. Typical applications include wireless infrastructure digitizers, IF sampling for SDR platforms, medical imaging front ends, and high-speed test & measurement digitizers. The 68-QFN footprint is shared across the KAD2710C/KAD2708L family, allowing design teams to migrate between 8-bit and 10-bit resolutions and between 105/170/210/275 MSPS speed grades without re-laying-out the PCB. When designing with the KAD2710C-27Q68, treat the exposed paddle as the primary thermal and ground return - use a continuous top-layer ground pour with at least 4 thermal vias to the inner ground plane. Provide a clean, low-noise 1.8 V AVDD and DRVDD using an LDO or ferrite-isolated switching converter; the SNR is degraded by any switching noise riding on the analog rail. This page synthesizes distributor pricing, drop-in alternatives within the KAD2710C family, and PCB layout considerations not collected in the datasheet summary - information gain beyond what a parametric search on DigiKey or Octopart provides.
KAD2710L-10Q68 - 10-Bit 105MSPS ADC, LVDS Output | Renesas
The Renesas KAD2710L-10Q68 is a 10-bit, 105 MSPS single-channel pipelined analog-to-digital converter with LVDS-compatible outputs, housed in a 68-pin QFN (10x10 mm) package. It belongs to the KAD2710L pin-compatible ADC family and integrates Intersil's proprietary FemtoCharge(TM) technology on a standard CMOS process to deliver low-power, high-dynamic-performance conversion. Headline parameters include 105 MSPS sample rate, 10-bit resolution, 55.6 dBFS SNR at fIN = 138 MHz, and 275 mW typical power consumption. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog input and produces a discrete-time digital code proportional to the input voltage. Pipelined ADCs are a high-speed ADC architecture that uses a cascade of low-resolution stages to achieve conversion rates from a few MSPS to several hundred MSPS, occupying a middle position in the converter hierarchy: Nyquist SAR -> pipelined ADC -> high-speed flash ADC, and they sit within the broader category of data acquisition ICs -> mixed-signal ICs -> integrated circuits. They are widely used in communications infrastructure, instrumentation, and imaging where both speed and resolution are required. Key features of the KAD2710L-10Q68 include a selectable divide-by-2 input clock divider, an over-range indicator for system-level gain control, LVDS digital outputs that simplify board-level routing and reduce EMI, and a single 1.8 V supply operation. The -10 speed grade limits the maximum sample rate to 105 MSPS, while the same pinout family extends up to 275 MSPS, enabling a single PCB to support multiple sampling-rate options. The 68-QFN exposed-paddle package provides a low thermal resistance path suitable for the device's continuous-conversion duty cycle. Internally, the KAD2710L uses a multi-stage switched-capacitor pipeline fronted by a track-and-hold, with proprietary FemtoCharge(TM) technology minimizing the size of the sampling capacitors. This reduces the input drive requirements and lowers kT/C noise contribution. An internal bandgap reference and proprietary bias network provide stable operation across the -40 C to +85 C industrial temperature range without external calibration, while a selectable LVDS or LVCMOS output mode allows the same converter to interface with either legacy CMOS or modern LVDS FPGA/ASIC receivers. Typical applications include cellular base-station IF digitizers, communications test equipment, low-cost portable oscilloscopes, and medical imaging front-ends. The wide LVDS eye-pattern tolerance makes the device well-suited to long PCB trace lengths to an FPGA, while the low power budget simplifies thermal design in dense multi-channel systems. When designing with this ADC, allocate adequate ground and power planes around the package and follow the recommended input drive network: a series resistor and shunt capacitor placed close to the analog input pin optimize SNR at high input frequencies. This page synthesizes distributor pricing, pin-compatible family alternatives (KAD2710C and KAD2708L families), and practical PCB layout notes that are not always presented together in the manufacturer datasheet.
LDC3114QPWRQ1 - 4-Ch Inductive Touch LDC, AEC-Q100 | TI
The Texas Instruments LDC3114QPWRQ1 is a 4-channel hybrid inductive touch and inductance-to-digital converter with a 0.16 ksps output rate and I2C interface, housed in a 16-pin TSSOP (PW) package and qualified to AEC-Q100 for automotive applications. The orderable part number LDC3114QPWRQ1 corresponds to the tape-and-reel packaging of the TSSOP-16 device, whose body measures 5.00 mm x 4.40 mm nominal and whose device marking is QDC3114. An inductance-to-digital converter (LDC) is a sensor interface IC that measures the shift in inductance of an external PCB coil caused by the proximity or deflection of a conductive metal target. Within the sensor signal-chain hierarchy, the LDC3114-Q1 sits as an analog front end (AFE) / data converter between passive inductive sensors and a host microcontroller, converting resonance frequency shifts into digital proximity or touch data transmitted over I2C. Key features include four independent sensing channels for multi-button or multi-target designs, contactless touch sensing through a wide variety of panel materials including metal, and inductance-based linear position sensing of metal targets. Because the coil can be implemented on a small PCB located behind the panel, the technology enables fully sealed, IP-rated HMI buttons with no mechanical wear. The hybrid architecture combines an LC oscillator front end with digital processing, outputting proximity/touch data at up to 0.16 ksps (160 samples per second) per the device description from DigiKey and datasheets.com. The I2C-compatible serial interface allows a single host to configure threshold registers and read per-channel touch status and raw proximity data. Typical applications include automotive HMI touch buttons (steering wheel, center console, door panels), precise linear position sensing of metal targets in automotive actuators, and industrial control panels requiring sealed, durable user interfaces. A key design consideration is coil and target geometry: sensitivity depends on coil size, target distance, and panel thickness, so the sensor coil should be tuned within the device's supported frequency range and thresholds calibrated per the TI datasheet guidance. This page synthesizes distributor pricing, same-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LMP91000SD/NOPB - Configurable AFE Potentiostat for Chemical Sensing | TI
The Texas Instruments LMP91000SD/NOPB is a programmable analog front-end (AFE) designed for micro-power electrochemical sensing applications, integrating a complete signal path between a chemical sensor and a microcontroller. It provides 1 channel, 8-bit register interface, operates from a 2.7V to 5.25V analog and digital supply, and is housed in a 14-pin WSON (4 mm x 4 mm) package. According to the TI product page, the device generates an output voltage proportional to the cell current, making it a drop-in read sensor analog subsystem for portable gas detection. An analog front-end (AFE) for electrochemical sensors is a mixed-signal IC that combines a potentiostat (a controlled-voltage/current bias circuit for the sensor working electrode), a transimpedance amplifier (TIA) that converts the sensor's picoampere-level current into a usable voltage, and a digital interface for microcontroller configuration. The LMP91000 sits inside the broader sensor signal chain hierarchy: electrochemical sensor -> AFE/potentiostat -> ADC -> microcontroller. Its programmability enables it to support multiple electrochemical sensors including 3-lead toxic gas sensors and 2-lead galvanic cells. Key features of the LMP91000SD/NOPB include a fully programmable transimpedance amplifier (TIA) gain, programmable bias voltage for the working electrode, programmable load resistor for the reference electrode, and an integrated temperature sensor to compensate for sensor temperature drift. The device also integrates a configurable I2C-compatible serial interface. Its low quiescent current makes it suitable for battery-powered portable gas detectors, and its small 4 mm x 4 mm WSON-14 footprint enables dense PCB layouts in wearable multi-gas sensor modules. Technically, the LMP91000 implements a true potentiostat topology using an op-amp-based control loop with MOSFET output stages, allowing the working electrode potential to be held precisely at the programmed bias voltage while sourcing or sinking the cell current. The integrated 8-bit DAC sets the bias voltage in 1 mV-typical steps, and the TIA gain is programmed through internal feedback resistor selection, giving the designer flexibility to match sensors with different current ranges (nA-level toxic gas sensors to mA-level bio-sensors). Typical applications include portable toxic gas detectors (CO, H2S, NO2), industrial safety monitors, breath analyzers, blood glucose meters, and environmental air-quality monitors. In a portable gas detector, the LMP91000 is placed between the 3-lead electrochemical sensor and a low-power MCU with an integrated ADC; the AFE handles biasing and current-to-voltage conversion while the MCU samples the voltage and applies temperature compensation. When designing with the LMP91000, ensure that the VDD decoupling capacitors are placed as close as possible to the analog and digital supply pins, and that the working, counter, and reference electrode traces are guarded to prevent leakage. The I2C SDA/SCL lines require pull-up resistors to VDD; consult the manufacturer's datasheet for the recommended pull-up value based on bus capacitance and clock speed. This page synthesizes distributor pricing, drop-in alternatives, and design notes not aggregated in any one manufacturer data sheet.
LTC1099CN#30369 - 8-Bit 2.5µs ADC w/ S/H | Analog Devices | DIP-20
The Analog Devices LTC1099CN#30369 is an 8-bit, 2.5 µs analog-to-digital converter (ADC) with an integrated sample-and-hold amplifier, housed in a 20-pin PDIP (N-20) through-hole package. It offers one input channel with a flash-style conversion architecture, supports full Nyquist-rate sampling, and is qualified for the commercial 0 °C to 70 °C operating range. The part is supplied in a 20-PDIP package with an input count of 1 and a flash converter topology per the manufacturer's product family specification. What is a flash ADC? A flash ADC is a parallel architecture where every possible quantization level is realized by a dedicated comparator bank feeding an encoder; conversion happens in a single step so latency is essentially one comparator delay, making flash ADCs the fastest ADC topology but resolution-limited by comparator count. Within the converter hierarchy, the LTC1099 sits between SAR (successive approximation) and full flash converters, using a sub-ranging / flash-front-end plus internal sample-and-hold to digitize high-bandwidth analog signals up to the full Nyquist rate. As a data-conversion IC, it belongs to the broader category of data acquisition > analog-to-digital converter > monolithic 8-bit ADC. Key features include a 2.5 µs typical conversion time (corresponding to 156 kHz 5V p-p input bandwidth), a built-in track-and-hold, microprocessor-compatible interface for direct connection to parallel-bus microcontrollers, single +5 V supply operation, and a flash-derived architecture. The integrated S/H allows the converter to handle fast-step inputs without requiring an external buffer, simplifying front-end design. The LTC1099 uses a sub-ranging flash architecture with internal reference generation and digital error correction. The integrated sample-and-hold sits at the analog front end and guarantees accurate acquisition of fast transient signals at the full Nyquist rate, which a discrete ADC + external amplifier combination often cannot match for input slew without careful layout. Typical applications include waveform digitizers, digital oscilloscope front-ends, video bandwidth digitizing up to 156 kHz, data-acquisition boards for industrial instrumentation, and process-control signal conditioning. It also serves in VCO/PLL feedback readback, ultrasound return-signal sampling, and any design requiring fast 8-bit throughput in a simple parallel microprocessor interface. When designing with the LTC1099, ensure clean analog and digital grounds (separated at the device pin) and place the supply bypass capacitor as close as possible to the VCC pin. The internal S/H drives input capacitance; source-impedance and bandwidth trade-offs should be evaluated when feeding the analog input directly from a sensor or filter. This page synthesizes distributor pricing, drop-in equivalents, and design notes not present in the bare manufacturer datasheet, including intent-specific FAQs and a comparison table for engineers migrating from earlier 8-bit ADCs.
LTC1418CN#PBF - 14-bit 200ksps Low Power SAR ADC | Analog Devices
The Analog Devices LTC1418CN#PBF (originally Linear Technology) is a low power, 200 ksps, 14-bit successive-approximation analog-to-digital converter (SAR ADC) offered in a 28-pin PDIP through-hole package. Key headline parameters include a 200 ksps sampling rate, 14-bit resolution, 15 mW typical power dissipation from a single 5 V or ±5 V supply, and selectable 14-bit parallel or serial data output format. The on-board high-performance sample-and-hold, precision reference, and internal timing keep external component count to a minimum, which simplifies board layout and reduces BOM cost. What is a SAR ADC? A successive-approximation analog-to-digital converter is a type of ADC that performs a binary search across an internal DAC to converge on the input voltage one bit per cycle. Within the broader hierarchy, this places SAR ADCs alongside pipelined, sigma-delta, and flash converters inside the data acquisition IC family. SAR converters deliver an excellent balance of speed, accuracy, and low power, which is why they remain a workhorse for industrial process control, instrumentation, and multiplexed data-acquisition front ends. Key features of the LTC1418CN#PBF include a built-in track-and-hold amplifier that eliminates the need for an external SHA, a typical differential non-linearity (DNL) of ±0.5 LSB, and bipolar/unipolar input capability when operated from ±5 V. Power-down mode reduces dissipation for battery-powered applications, and the wide analog input range (0 V to 5 V single-ended, ±5 V true bipolar) gives designers flexibility when digitizing transducer or sensor signals. Architecturally, the LTC1418 uses a charge-redistribution DAC array combined with a precision buried-Zener reference and auto-calibrated switch-capacitor front end. At 200 ksps, it sustains full 14-bit performance without missing codes, and the serial/parallel interface allows the same silicon to drop into either high-pin-count microcontroller buses or low-pin-count SPI controllers. Typical applications include industrial process-control data acquisition boards, portable or battery-powered instrumentation, multiplexed sensor read-back, and digital signal processing front ends. The 5 V single-supply capability also makes it suitable for legacy 5 V-only embedded designs. Designers should note that the LTC1418 is in the process of being discontinued; an SSOP-28 replacement (LTC1418CG#PBF) exists but is NOT pin-to-pin compatible with the DIP-28. Plan PCB rework or substitute silicon if the DIP-28 supply runs out. This page synthesizes Analog Devices datasheet data, distributor stock and pricing from DigiKey, and practical design considerations not found on manufacturer product pages.
LTC1605-1CN#PBF - 16-Bit, 100ksps SAR ADC, 0-4V Input, 28-PDIP | Analog Devices
The Analog Devices LTC1605-1CN#PBF is a 16-bit, 100ksps successive-approximation analog-to-digital converter that operates from a single 5V supply, drawing only 55mW (typical) and housed in a 28-pin PDIP through-hole package. It integrates a sample-and-hold amplifier, a precision internal reference, a switched-capacitor 16-bit SAR ADC core, and a trimmed internal clock, providing a complete data-acquisition solution in a single IC. A successive-approximation register (SAR) ADC is a type of analog-to-digital converter that performs a binary search across the input voltage using an internal DAC and comparator; SAR ADCs are valued for low latency, deterministic conversion time, and excellent DC accuracy with no pipeline delay, making them well-suited for multiplexed data acquisition, industrial process control, and precision instrumentation where a single-channel, low-noise conversion is required. Key features include a 0V to 4V true-differential analog input range (industry-standard unipolar), ±2.0 LSB maximum integral nonlinearity (INL), guaranteed 16-bit no-missing-codes over temperature, and a flexible parallel data output interface (16-bit wide or two-byte) that connects directly to microprocessors, DSPs, and FIFOs. The internal 2.5V reference is trimmed for low drift; an external reference may be applied for higher absolute accuracy over temperature. A CONVST input and BUSY (EOC) output simplify handshaking with external logic. Architecturally, the device uses a charge-redistribution switched-capacitor DAC paired with a low-noise comparator and an SAR control engine; the input sample-and-hold acquires the signal on the rising edge of CONVST and the conversion completes in 8µs, after which data is presented on the parallel port with BUSY going low. Single 5V operation eliminates the negative supply required by many legacy bipolar ADCs, simplifying board power design. Typical applications include industrial process control and multi-channel data-acquisition front ends (paired with an external MUX), precision weighing scales and load-cell digitizers, bench-top and laboratory instrumentation, medical diagnostic equipment, and high-accuracy temperature or strain-gauge measurement systems. The LTC1605-1CN#PBF's commercial 0°C to 70°C operating range suits laboratory, factory-floor, and bench environments. When designing with this part, place 10µF (or larger) bypass capacitors close to the AVdd and DVdd pins and respect a star-ground topology between the analog input ground return and digital ground to avoid code-dependent noise coupling into the reference. The 28-PDIP package is convenient for prototype boards, sockets, and through-hole assembly but is not recommended for new high-density surface-mount designs - consider the SSOP-28 (LTC1605-1CG#PBF) for SMT layouts. This page synthesizes distributor pricing, true drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC1605-1IN#PBF - 16-Bit 100ksps SAR ADC | Analog Devices
The Analog Devices LTC1605-1IN#PBF is a 16-bit, 100 ksps successive-approximation analog-to-digital converter (SAR ADC) in a 28-pin PDIP (N) through-hole package. According to the Analog Devices datasheet, the device draws only 55 mW (typical) from a single 5 V supply, includes a sample-and-hold front-end, a precision internal reference, and a trimmed internal clock, providing a complete 16-bit data-acquisition solution in one IC. The unipolar input range is 0 V to 4 V (LTC1605-1 variant; LTC1605-2 variant covers ±4 V bipolar). The converter features a microprocessor-compatible 16-bit or two-byte parallel output port for direct connection to data buses and DSP/microcontroller interfaces. A SAR ADC is a successive-approximation-register analog-to-digital converter that uses a binary-search algorithm and an internal capacitive DAC to resolve the input voltage one bit at a time per clock cycle. SAR ADCs occupy the middle ground between delta-sigma (high resolution, low speed) and flash (very high speed, low resolution) architectures. They are the dominant choice for 12-16 bit industrial data-acquisition systems running at 10 ksps to 1 Msps, particularly when deterministic latency and a parallel/serial output are required. The LTC1605-1IN#PBF inherits the lineage of the industry-standard LTC1605 family, all of which share the same 28-pin pinout and timing characteristics for drop-in upgrades. Key features include 16-bit no-missing-codes performance, 86 dB typical signal-to-noise ratio, a 100 ksps sampling rate, and an external reference option for systems that require better temperature drift than the internal 2.5 V reference provides. The 28-pin PDIP package is through-hole, simplifying prototyping and field replacement for industrial instrumentation. Typical applications include industrial process control, multi-channel data-acquisition boards, weigh-scale and load-cell digitizers, panel meters, instrumentation front-ends, and bench-top test-and-measurement equipment. The 5 V single-supply operation and parallel data port allow direct connection to legacy parallel-signal processors and modern microcontrollers/DSPs without additional level translation. When designing with the LTC1605-1IN#PBF, ensure the analog input is buffered if the source impedance exceeds the datasheet-specified value, and decouple VDD with a 10 µF tantalum in parallel with a 0.1 µF ceramic placed within 1 cm of the supply pin. The #PBF suffix indicates lead-free (Pb-free) and RoHS-compliant construction, qualifying the part for modern and export-controlled designs.
LTC1605-2CN#PBF - 16-Bit 100ksps ±4V Bipolar SAR ADC | ADI
The Analog Devices LTC1605-2CN#PBF is a 16-bit, 100 ksps successive-approximation analog-to-digital converter that operates from a single 5 V supply and dissipates only 55 mW typical. Housed in a 28-pin PDIP through-hole package, the device integrates a sample-and-hold front end, a precision internal reference, a switched-capacitor SAR core, and a trimmed internal clock, enabling a complete 16-bit conversion solution in one IC. The -2 suffix denotes a bipolar ±4 V analog input range, which makes the part well suited to industrial signal acquisition that uses a true bipolar front end. A successive-approximation register (SAR) ADC is a type of data converter that performs one binary bit decision per conversion cycle, using an internal comparator, DAC, and successive-approximation logic. SAR converters sit in the broader ADC hierarchy between delta-sigma (high resolution, low speed) and flash (high speed, low resolution), and are favored for multiplexed data-acquisition systems because they perform a complete, deterministic conversion in N clock cycles with no pipeline latency. The LTC1605-2 exemplifies this architecture with its single-shot, software-controlled conversion cycle. Key specifications of the LTC1605-2 include 16-bit resolution with no missing codes, ±4 V bipolar input range, 100 ksps sampling rate, parallel data interface, ±2.5 LSB INL typical, and integrated reference. The internal clock and the integrated reference eliminate external ADC support components, simplifying the analog front end. Because the part is single-supply 5 V with a true bipolar differential input stage, designers can connect the output of a ±4 V instrumentation amplifier directly to the ADC inputs with minimal signal conditioning. The architecture uses a charge-redistribution switched-capacitor DAC inside the SAR loop, a technique that yields excellent DC linearity for instrumentation workloads. The integrated 4.096 V reference is trimmed at the factory, so the converter achieves specified noise and INL performance without external reference components, although a 2.2 µF bypass close to the REF pin is required for full accuracy. Typical applications include process-control analog input modules, industrial PLC analog front ends, precision data-acquisition boards, multichannel instrumentation front ends with bipolar signals, and laboratory instrumentation that requires 16-bit accuracy without high-speed throughput. Designers in these segments value the deterministic conversion latency and the simple parallel read interface. When designing the PCB, place the 2.2 µF REF bypass capacitor and the 10 µF VCC decoupling capacitor as close to the IC pins as possible. Use a ground plane under the analog section and keep digital return currents out of the analog ground path. Use the S/H (sample-and-hold) pin or the CS and RD signals to start conversions; the LTC1605-2 does not auto-run. This page synthesizes distributor pricing, pin-compatible ADI alternatives in the same 28-PDIP footprint, and practical layout notes beyond the manufacturer datasheet, helping engineers evaluate LTC1605-2CN#PBF for drop-in upgrades, second sources, and bipolar-input acquisition channels.
LTC1605ACN - 16-Bit 100ksps ADC with Bipolar ±10V Input | Analog Devices
The Analog Devices LTC1605ACN is a 16-bit, 100 ksps sampling analog-to-digital converter (ADC) housed in a 28-pin PDIP through-hole package. It draws only 55 mW (typical) from a single +5 V supply, accepts a bipolar ±10 V input range, and features an internal precision reference with trimmed internal clock for easy standalone operation. An analog-to-digital converter (ADC) is a data-converter integrated circuit that converts a continuous analog voltage into a discrete digital code, occupying a key position in the signal-chain hierarchy: transducer -> analog front end / signal conditioning -> ADC -> digital processor. Successive-approximation register (SAR) ADCs in particular combine a sample-and-hold, precision reference, switched-capacitor DAC and SAR logic to deliver one conversion per clock, with low latency and deterministic behavior well suited to multiplexed data acquisition and industrial instrumentation. Key features of the LTC1605ACN include ±2.0 LSB (max) INL over temperature, guaranteed 16-bit no missing codes, a microprocessor-compatible 16-bit or two-byte parallel output port, and the ability to be driven by an external reference when higher absolute accuracy is required across temperature. Synchronous sampling and a wide input range let it directly digitize industrial ±10 V signals without external scaling amplifiers. The device uses a precision bandgap reference and trimmed internal clock, simplifying the analog front end to a simple RC input network plus an external reference option for temperature-stable accuracy. Successive-approximation architecture yields deterministic latency and excellent DC linearity for instrumentation applications. Typical applications include industrial process control data acquisition boards, multichannel multiplexed data loggers, instrumentation and measurement front ends, and legacy factory automation I/O subsystems. The bipolar ±10 V range lets it connect directly to legacy industrial sensors and 4-20 mA loop resistors. Design with the device by ensuring the analog input pin sees a low-impedance buffer or RC network matching the ADC's switched-capacitor front end, and by tying REFCOMP to a 10 µF bypass capacitor near the pin to minimize reference noise. Latency is one conversion clock, simplifying timing analysis for sequential multiplexer scans.
LTC1605AIN - 16-Bit 100ksps Sampling ADC ±10V | Analog Devices
The Analog Devices LTC1605AIN is a 16-bit, 100ksps sampling analog-to-digital converter that draws only 55 mW (typical) from a single 5V supply, packaged in a 28-pin SSOP. It integrates a sample-and-hold amplifier, a precision internal reference, a switched-capacitor successive-approximation ADC core, and a trimmed internal clock, providing a complete bipolar-input ADC solution. The bipolar analog input range is ±10V, suitable for industrial process control, instrumentation, and signal-isolation data-acquisition front-ends. An ADC (analog-to-digital converter) is a semiconductor device that converts a continuous analog voltage or current into a discrete digital code; sampling ADCs additionally include a sample-and-hold front-end that captures and freezes the input at a precise moment so that the conversion can proceed without aliasing. In the broader component hierarchy, the LTC1605AIN is a successive-approximation-register (SAR) ADC, a sub-category of data converters that sits under interface/ADC ICs in mixed-signal systems. SAR ADCs are favored for their deterministic latency, low power consumption, and excellent DC accuracy compared with delta-sigma or pipeline architectures, making them ideal for multiplexed data-acquisition systems. Key features include ±2.0 LSB maximum integral nonlinearity, guaranteed no missing codes at 16 bits, ±10V true bipolar input range from a single 5V supply, and a 55 mW typical power dissipation. The part is specified over the commercial 0°C to 70°C operating range, with the 'N' suffix indicating an SSOP-28 package and 'I' indicating the commercial temperature grade. The internal reference and trimmed clock eliminate the need for external components, simplifying board layout and reducing BOM cost. Architecturally, the LTC1605AIN combines a fast bipolar-input track-and-hold with a charge-redistribution SAR core and an on-chip reference. The trimmed internal clock removes the requirement for an external timing source, and the parallel output interface delivers conversion results in a single read cycle. The 100ksps throughput makes it well suited to multiplexed multi-channel systems where each channel can still be sampled at several kHz. Typical applications include industrial process control and instrumentation, multiplexed data-acquisition systems, signal-isolation front-ends, and portable or battery-powered test equipment. The ±10V bipolar input makes it a natural drop-in for legacy 5V-only signal chains migrating from older bipolar ADC designs. When designing with this part, allocate adequate board area for the analog input anti-alias filter and bypass the supply pin with a 10 µF tantalum plus 0.1 µF ceramic capacitor within 10 mm of the device. The analog and digital grounds should be tied at a single star point beneath the IC to minimize noise coupling from the parallel output bus into the sensitive input front-end. This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the Site MPN list, and practical design notes not found in the manufacturer datasheet, enabling faster BOM selection for engineers maintaining or designing-in the LTC1605AIN.
LTC1605CN#PBF - 16-Bit 100ksps SAR ADC, ±10V Bipolar | ADI
The Analog Devices (formerly Linear Technology) LTC1605CN#PBF is a 100 ksps, 16-bit sampling analog-to-digital converter (ADC) that draws only 55 mW (typical) from a single 5 V supply, housed in a 28-pin PDIP (through-hole) package. The device integrates a sample-and-hold front end, a precision buried-zener reference, a switched-capacitor successive-approximation ADC core, and a trimmed internal clock, providing a complete data-acquisition front end in one IC. A successive-approximation register (SAR) ADC is a precision converter architecture that performs a binary search across an internal DAC for each conversion, achieving deterministic low-latency (one conversion cycle) results with no pipeline delay. SAR ADCs are widely used in industrial, instrumentation, and process-control applications where DC accuracy, high linearity, and excellent AC performance at moderate sampling rates are required. The LTC1605 sits in the precision SAR family alongside the 14-bit LTC1410 and 12-bit LTC1290, sharing a common analog front-end philosophy and pinout philosophy. Key specifications include 16-bit resolution with no missing codes, ±2.0 LSB maximum integral nonlinearity (INL), ±10 V true-bipolar input range from a single 5 V supply, 100 ksps sampling rate, and 55 mW typical power dissipation. The integrated reference eliminates external reference components, simplifying the bill of materials. The parallel data interface allows direct connection to microprocessors, FPGAs, or DSPs without serial-deserialization glue logic. Typical applications include industrial process control, multiplexed data-acquisition systems, precision instrumentation, seismic and weigh-scale digitizers, spectrum and vibration analysis front ends, and bench-top DMM front ends. The ±10 V true-bipolar input is a key differentiator, allowing direct digitization of industrial sensor outputs (4-20 mA loops scaled to voltage, strain-gauge bridges, thermocouple amplifiers) without external signal conditioning. When designing with the LTC1605, allocate at least 8 analog input pins plus dedicated AGND and DGND pins, and follow ADI's recommended four-layer board with separate analog and digital ground planes joined at a single point near the IC. The internal reference requires a 10 µF bypass capacitor on the REFCOMP pin for optimal linearity. This page synthesizes distributor pricing, drop-in 28-PDIP alternatives (LTC1605IN, LTC1605-1CN, LTC1605-2CN), and practical design notes not aggregated on any single manufacturer or distributor page.
LTC1650AIN#PBF - 16-Bit Low-Glitch Voltage Output DAC | ADI
The Analog Devices LTC1650AIN#PBF is a 16-bit, low-glitch, rail-to-rail voltage-output digital-to-analog converter (DAC) housed in a 16-pin PDIP through-hole package, qualified to the industrial -40C to +85C temperature range. It integrates a precision R-2R ladder, an output buffer amplifier, and a three-wire cascadable serial (SPI/MICROWIRE-compatible) interface, delivering 16-bit monotonic performance over temperature with a glitch impulse of just 2 nV-s. The DAC operates from dual plus/minus 5 V supplies and dissipates approximately 50 mW, with the output swing defined by REFLO and REFHI reference inputs that can be tied for unipolar or bipolar modes. A digital-to-analog converter (DAC) is a data-conversion integrated circuit that translates a digital code word into a precisely scaled analog voltage or current. Within the broader data-converter family (ADC and DAC), this part belongs to the precision narrow-DC voltage-output DAC category, sitting under the hierarchy: DAC -> data converter -> mixed-signal IC -> semiconductor. The LTC1650AIN#PBF specifically targets low-glitch, low-noise, buffered voltage-output applications where a clean step transition and rail-to-rail swing are critical. Key differentiating specifications include 2 nV-s glitch impulse, 30 nV/sqrt(Hz) noise spectral density, 16-bit guaranteed monotonicity, and a true rail-to-rail output buffer that swings to within millivolts of either supply rail. The cascadable three-wire serial interface allows multiple LTC1650 devices to share a single SPI bus by daisy-chaining the DOUT pin into the next device's DIN pin, simplifying multi-axis or multi-channel designs. Architecturally, the device combines a thin-film R-2R ladder network for INL/DNL linearity with an on-chip output op-amp capable of driving 2 kohm/100 pF loads. The internal reference inputs (REFHI/REFLO) decouple the output range from the supply rails, enabling asymmetric spans such as 0 to 4.096 V for unipolar or plus/minus 4.096 V for bipolar operation. Typical applications include industrial process control calibration, automated test equipment (ATE) waveform generation, digitally controlled offset and gain trimming, programmable voltage references, and motor-control setpoint generation. The wide output swing and low glitch make the LTC1650AIN#PBF a strong fit where each code transition must not couple into downstream signal-chain stages. When designing with this part, place 0.1 uF decoupling capacitors close to AVDD, DVDD, and AVSS pins and route REFHI/REFLO traces as a differential pair. Keep the analog ground (AGND) and digital ground (DGND) joined at a single star point beneath the IC to preserve the 16-bit linearity. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-level design guidance not found in the manufacturer datasheet alone, giving engineers a single reference for evaluation and sourcing.
LTC1657LIGN - 16-Bit Rail-to-Rail DAC, 28-SSOP | Analog Devices
The Analog Devices LTC1657LIGN is a 16-bit rail-to-rail micropower parallel digital-to-analog converter (DAC) housed in a 28-lead SSOP (GN) package. It operates from a single 2.7 V to 5.5 V supply, delivers monotonic 16-bit performance over the industrial temperature range, and provides a deglitched rail-to-rail voltage output stage that swings within 8 mV of either rail. Typical supply current is 650 uA, making it one of the lowest-power 16-bit parallel DACs in its class. A digital-to-analog converter (DAC) is an integrated circuit that converts a digital code word into a precisely defined analog voltage or current. Within the broader signal-chain taxonomy, the LTC1657 belongs to the precision converter family -> data converter -> mixed-signal IC -> semiconductor. The LTC1657 specifically targets low-power, high-resolution applications where a parallel microprocessor-style interface is preferred for fast code updates without serial-clock overhead. Key features include guaranteed 16-bit monotonicity over temperature, maximum DNL of ±1 LSB, internal power-on reset to zero scale, an asynchronous CLR pin for output forcing, and a built-in 1.25 V reference accessible at the REFOUT pin (LTC1657L variant). The device accepts a parallel 16-bit word and updates the output on the rising edge of CS/WR. Settling time to ±1 LSB is specified at 20 us for a full-scale step. The SSOP-28 footprint is industry-standard and compatible with the LTC1450 12-bit family, providing an upgrade path for existing designs. Architecturally, the LTC1657LIGN uses a resistor-string (R-2R ladder) topology with an output buffer amplifier, ensuring inherently monotonic operation and low glitch impulse. The reference input can be driven externally or tied to the internal 1.25 V bandgap via REFOUT, providing design flexibility for both ratiometric and absolute-output applications. Typical applications include industrial process control, digital offset and gain adjustment, automatic test equipment (ATE) programmable stimulus, audio attenuators with parallel volume control, and portable battery-powered instrumentation where the 650 uA quiescent current extends operating life. The wide supply range and rail-to-rail output maximize signal swing on low-voltage rails. When designing with this device, ensure the REFLO pin is tied to GND and that bypass capacitors of 0.1 uF and 10 uF are placed close to VCC. The asynchronous CLR pin must be held high during normal operation to avoid unintended reset events. Designers migrating from the LTC1450 12-bit family benefit from pin-compatibility and only need to extend the data bus from 12 to 16 bits. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for evaluation, sourcing, and PCB layout reuse.
LTC1856IG - 16-Bit, 100ksps, 8-Ch ±10V ADC | Analog Devices
The Linear Technology/Analog Devices LTC1856IG is a 16-bit, 100 ksps, 8-channel successive-approximation analog-to-digital converter (SAR ADC) housed in a 28-pin SSOP (G) package. According to the Analog Devices LTC1854/LTC1855/LTC1856 datasheet, the device operates from a single 5 V supply, integrates an 8-channel analog input multiplexer programmable for single-ended inputs, differential pairs, or a combination of both, and provides ±30 V fault protection on every channel so that a transient on one channel does not disturb conversions on the remaining channels. A successive-approximation register (SAR) ADC is a type of data converter that performs a binary search through an internal capacitive DAC to resolve an analog input in N clock cycles, where N is the resolution in bits. SAR ADCs offer deterministic latency, no pipeline delay, and excellent DC accuracy, which makes them well suited for multiplexed data-acquisition systems, industrial process control loops, and instrumentation that scans many channels at modest rates. The LTC1856 sits inside this hierarchy as a low-power, multi-channel, 16-bit precision SAR converter with integrated input protection. Key specifications include 16-bit resolution (LTC1856) within the LTC1854/55/56 family, ±3 LSB maximum INL for the LTC1856, a 5 µs maximum conversion time, a 100 ksps guaranteed sampling rate, single 5 V supply operation, and an integrated shutdown mode for power-sensitive multiplexed applications. The internal oscillator is trimmed for low aperture uncertainty and consistent conversion timing across the operating range. The 8-channel multiplexer is software-configurable for 8 single-ended inputs, 4 differential pairs, or any mixed combination; a fault on any one input channel does not corrupt conversions on the others because each input is independently over-voltage protected to ±30 V. A hardware shutdown pin reduces supply current between conversions for battery-powered or thermocouple-scanning systems. Typical applications include industrial process control and SCADA data acquisition modules, multi-channel thermocouple and RTD temperature monitoring with cold-junction compensation, portable and bench-top multi-meter instruments, multichannel analog front-ends for PLCs, and automated test equipment requiring 16-bit DC accuracy across many input ranges. The ±10 V true-bipolar input range (with 5 V supply) makes the LTC1856IG drop-in compatible with the output swing of legacy ±10 V instrumentation and industrial sensors. When designing with this ADC, add a 10 µF/0.1 µF bypass pair on the 5 V pin and place the part close to the analog input protection network. Use a low-impedance input buffer for high source-impedance sensors to preserve 16-bit accuracy. The internal reference must be decoupled per the datasheet to avoid gain error; an external reference can be driven if higher accuracy or a lower temperature coefficient is required. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer's datasheet, including verified 28-SSOP footprint cross-references and a side-by-side specification comparison.
LTC2107IUK - 16-Bit 210Msps High-Performance ADC | Analog Devices
The Analog Devices LTC2107IUK is a 16-bit, 210 Msps high-performance pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm, exposed pad) package, designed specifically for the most demanding receiver applications such as software-defined radio (SDR) and multi-channel GSM base stations. Combining high sample rate, low noise and high linearity, the part delivers SNR = 80 dBFS and an industry-leading SFDR performance that enables a new generation of direct-sampling digital radio designs. What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture that converts an analog input by passing the signal through a cascade of low-resolution flash sub-converter stages, each resolving a few bits and feeding the residue to the next stage. Pipelined ADCs sit within the broader hierarchy of Nyquist-rate data converters (successive-approximation, flash, pipelined) and serve as the workhorse for widebandwidth communications, instrumentation and radar signal chains that demand both high sampling rate and 12-16 bit resolution. Key features of the LTC2107IUK include differential input architecture optimized for IF sampling, 210 Msps conversion rate, on-chip buffer and programmable digital gain, low-jitter clock interface accepting CMOS/LVDS/ PECL inputs, and LVDS/SPI-configurable output modes for flexible data capture. The 80 dBFS SNR and high spurious-free dynamic range ensure clean digitization of multi-carrier waveforms without raising the receiver noise floor. Architecturally, the LTC2107IUK integrates a precision front-end sample-and-hold, multi-bit pipelined core, on-chip voltage reference, and output error correction. The exposed-pad QFN-48 package provides a low thermal resistance path (~30 C/W θJA on a 4-layer JEDEC PCB) so the part can sustain full-speed operation in dense radio boards without external heatsinking. Typical applications include software-defined radio receivers, multi-carrier GSM/EDGE and LTE base-station receivers, broadband instrumentation, radar/EW intermediate-frequency digitization, and high-speed medical imaging front-ends. The wide input bandwidth and direct IF sampling capability let designers replace traditional analog mixer/IF-filter chains with a single ADC at lower BOM cost. When designing with the LTC2107IUK, pay attention to input common-mode voltage, transformer coupling, and clock jitter. An aperture jitter of 200 fs RMS guarantees SNR at full-rate input frequencies; designers must keep total system clock jitter below ~500 fs RMS to preserve dynamic range. A 4-layer PCB with continuous ground plane and proper LVDS output routing is essential for EMI compliance.
LTC2122CUK - Dual 14-bit 170Msps ADC with JESD204B | ADI
The Analog Devices LTC2122CUK is a dual 14-bit 170Msps analog-to-digital converter with JESD204B serial outputs, housed in a 48-pin QFN (7x7 mm) package. It supports 2-channel simultaneous sampling at up to 170Msps per channel, with 70dBFS SNR and 90dBFS spurious-free dynamic range (SFDR) for high-frequency, wide dynamic range signal acquisition. What is a JESD204B ADC? JESD204B is a high-speed serial interface standard (JEDEC JESD204B, revision 2011) that converts parallel ADC data into serialized lanes running at multi-gigabit rates. It reduces PCB routing congestion by replacing wide parallel LVDS buses with 1-8 differential lanes, simplifying layout for multi-Gsps converters used in communications, radar, and test instrumentation. As a pipelined dual-channel converter with serial outputs, the LTC2122CUK sits in the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor. Key features include a 1.25GHz analog input bandwidth that enables reliable IF under-sampling, integrated input buffers to ease front-end matching, and sub-clock jitter performance optimized for communications transceivers. The pipelined architecture delivers low latency and deterministic sample timing across both channels, simplifying multi-channel synchronization in MIMO and phased-array systems. Technical depth: the LTC2122CUK uses a calibrated pipelined core per channel with on-chip dither, achieving 70dBFS SNR and 90dBFS SFDR with input tones in the Nyquist zone. The JESD204B subclass 1 interface supports deterministic latency and supports 1 to 4 lanes per ADC, with link speeds up to 4.5Gbps per lane depending on configuration. The 7x7 mm QFN-48 package exposes a thermal pad for low-junction-rise operation. Typical applications include multi-channel wireless communications receivers, multiband radar and phased-array digitizers, broadband data acquisition systems, and high-end test and measurement instrumentation. The dual-channel simultaneous-sampling capability is particularly valuable in diversity receivers and I/Q signal paths. When designing with this part, ensure the JESD204B link parameters (L, M, F, K) match the receiving FPGA or ASIC SerDes, and provide a low-jitter clock with <300fs RMS jitter to preserve SNR. Decoupling on each supply pin must use a 0.1uF ceramic placed within 3 mm of the pin. This page synthesizes distributor pricing, drop-in equivalents, and practical design notes not consolidated on the manufacturer datasheet.
LTC2122IUK - Dual 14-Bit 170Msps ADC w/ JESD204B | ADI
The Analog Devices LTC2122IUK is a dual-channel, simultaneously-sampling 14-bit 170 Msps analog-to-digital converter (ADC) with JESD204B serial outputs, housed in a 48-lead QFN (7x7 mm) package with exposed pad. According to the LTC2122 datasheet, the converter delivers 70 dBFS SNR and 90 dBFS spurious-free dynamic range (SFDR) while supporting 1.25 GHz analog input bandwidth for IF/RF undersampling. The device operates from a 1.7V to 1.9V analog supply and integrates an on-chip clock-duty-cycle stabilizer, reducing external PLL requirements for high-speed communication systems. Each channel features a differential input front-end with 600 MHz full-power bandwidth, supporting wideband signal chains from DC to beyond 200 MHz of input frequency. A pipelined ADC architecture uses a high-speed, multi-stage switched-capacitor structure with digital error correction, allowing the LTC2122 to maintain 14-bit linearity up to 170 Msps. Dual-channel simultaneous sampling eliminates inter-channel skew, critical for MIMO receivers, phased-array radar, and diversity antenna systems. The JESD204B serial interface transports the digitized data using up to 4 lanes with 8b/10b encoding, deterministic latency, and embedded clock recovery, which minimizes board routing complexity compared to LVDS parallel interfaces. An on-chip SYSREF input supports deterministic latency for multi-device synchronization in large-channel-count systems. The LTC2122 targets demanding communications applications including LTE and multi-carrier GSM base-station receivers, software-defined radio, cable infrastructure head-end digitization, and high-density MIMO systems. Its 70 dBFS SNR and 90 dBFS SFDR at 170 Msps enable the receiver to digitize a 60 MHz LTE carrier with margin for adjacent-channel blocker rejection. The 1.25 GHz input bandwidth also supports undersampling of L-band and S-band signals, reducing the number of downconversion stages in the signal chain. The 48-QFN (7x7) exposed-pad package provides a low thermal resistance path, allowing operation across the industrial -40C to +85C temperature range without derating at the rated sample rate. For PCB layout, place 0.1uF and 10nF ceramic decoupling capacitors within 5 mm of each supply pin, with the exposed pad soldered to a continuous ground plane. Route the JESD204B serialized lanes as length-matched 100 ohm differential pairs with controlled 50 ohm single-ended impedance, and keep AC-coupled capacitors within 5 mm of the transmitter pins to meet the JESD204B eye-mask specification.
LTC2123CUK - 14-Bit 250Msps Dual ADC, JESD204B | ADI
The Analog Devices LTC2123CUK is a dual-channel, simultaneous-sampling 14-bit, 250 Msps analog-to-digital converter with JESD204B serial outputs, housed in a 48-pin QFN (7x7 mm) package. It is designed for digitizing high-frequency, wide dynamic range signals and is targeted at demanding communications, radar, and test-and-measurement receivers. According to the Analog Devices LTC2123 datasheet, the converter delivers 70 dBFS SNR and 90 dBFS spurious-free dynamic range (SFDR) with a 1.25 GHz input bandwidth that supports accurate IF under-sampling. A pipelined ADC is a multi-stage converter that uses low-resolution flash sub-ADCs and a digital correction network to digitize an analog signal at very high sample rates while maintaining fine amplitude resolution. Within the broader converter taxonomy, pipelined ADCs sit between high-speed flash ADCs and lower-power successive-approximation ADCs, and they are the most widely used architecture for sampling rates from ~50 Msps to several hundred Msps. The LTC2123CUK belongs to this high-speed pipelined class and is positioned for multi-lane serial-data transport via the JEDEC-standardized JESD204B serial interface. Key features include a 14-bit resolution with 250 Msps sample rate, dual simultaneously-sampling analog inputs, an integrated clock and sample-and-hold front end, a 1.25 GHz analog input bandwidth, and a JESD204B-encoded serial data interface that minimizes board-routing complexity. The device operates from standard 1.8 V supply rails and includes internal dithering to improve low-amplitude linearity for small-signal RF work. The LTC2123CUK architecture uses a multi-stage switched-capacitor pipeline with proprietary calibration that flattens the noise and linearity curves across the Nyquist band. By running at 250 Msps from a single 1.8 V supply, the part achieves an SNR floor (70 dBFS) and SFDR (90 dBFS) that previously required dual-supply 5 V parts. The JESD204B Subclass 1 output supports deterministic latency and up to 4 lanes, which simplifies FPGA/ASIC capture when multiple converters must be phase-coherent. Typical applications include multi-antenna diversity receivers, IF digitizers for wireless base stations, broadband instrumentation, phased-array radar signal chains, and high-speed data acquisition test systems. The wide input bandwidth allows straightforward sampling of intermediate frequencies in the second or third Nyquist zone. When designing with the LTC2123CUK, plan the PCB layout for 50 ohm controlled-impedance analog inputs and tightly decouple the two 1.8 V supply domains (analog AVDD and digital DVDD/DRVDD) close to the package. The exposed thermal pad must be soldered to a continuous ground island to keep junction temperature within the commercial 0 to 70 C operating range. This page synthesizes distributor pricing, drop-in compatible variants from the same LTC2123 family, application context, and practical design notes not collected in any single manufacturer document.
LTC2123IUK - 14-Bit 250Msps Dual ADC w/ JESD204B | ADI
The Analog Devices (formerly Linear Technology) LTC2123IUK is a dual 14-bit, 250 Msps analog-to-digital converter with JESD204B serial outputs, housed in a 48-lead QFN (7 mm x 7 mm) package with exposed pad. It is built on a high-performance pipelined architecture and provides two simultaneously-sampling ADC channels on a single die, supporting communications-grade signal chain designs. The listed 1ku price starts at $177.20 per part per the Analog Devices product page. An ADC (Analog-to-Digital Converter) is a mixed-signal data converter IC that samples continuous analog voltages and emits a discrete digital code for downstream processing. High-speed pipelined ADCs are positioned at the top of the converter hierarchy and serve as the gateway between RF/IF analog front-ends and FPGA/DSP digital processing in the signal chain - they are essential for software-defined radio, multi-antenna base stations, and electronic test & measurement instrumentation. Key features of the LTC2123 family include 14-bit resolution, 250 Msps sampling per channel, dual-channel simultaneous sampling, JESD204B serial output protocol for high-speed board-level data transfer, low-jitter clock input, internal dither for spurious-tone improvement, and selectable digital output modes. The 48-QFN package exposes a thermal pad for low-theta-JA board cooling and is qualified for the -40C to +85C industrial temperature range. The pipelined architecture distributes the conversion across cascaded low-resolution stages with redundant bit alignment, achieving high throughput at moderate power per channel while maintaining excellent AC linearity (SFDR, SNR). The integrated JESD204B interface replaces wide parallel LVDS buses with a serialized lane pair, dramatically simplifying FPGA-ADC board routing and improving multi-board synchronization via deterministic latency. Typical applications include LTE/4G/5G base-station receivers, multi-carrier software-defined radio, phased-array radar and EW systems, high-density MIMO digitizers, automated test equipment digitizer cards, and medical imaging front-ends. In all of these, the LTC2123's simultaneous dual-channel 250 Msps operation delivers the per-channel throughput required for direct IF sampling. When designing with this device, allocate a low-noise PLL clock source (e.g., ADF4350/ADF4106), maintain 100-ohm differential input impedance via tight-edad interface, and lay out the JESD204B lanes at length-matched controlled impedance per the JEDEC JESD204B specification to meet the required signal-integrity eye at the receiver. Verify with the manufacturer's evaluation kit (DC2154 or similar) before production.
LTC2140CUP-12 - 12-Bit 25Msps Dual-Channel ADC | Analog Devices
The Analog Devices LTC2140CUP-12 is a 2-channel simultaneous-sampling 12-bit analog-to-digital converter (ADC) designed for digitizing high-frequency, wide-dynamic-range signals, supporting up to 25 Msps per channel in a 64-pin QFN (9 mm x 9 mm) package. It belongs to the LTC2142-12 / LTC2141-12 / LTC2140-12 family, which share a common datasheet and differ primarily in maximum sampling rate (65/40/25 Msps respectively), enabling software-compatible scaling across pipelined ADC designs. An ADC (Analog-to-Digital Converter) is a semiconductor device that samples a continuous analog voltage and converts it to a discrete digital code. In the system hierarchy, an ADC sits between an analog front-end (amplifiers, filters, sensors) and a digital signal processor (DSP, FPGA, or microcontroller). Pipelined ADCs such as the LTC2140CUP-12 use a multi-stage architecture that achieves high sample rates with moderate power consumption by interleaving low-resolution stages, trading slightly higher latency for the ability to capture multi-MHz bandwidth signals at low cost. Key features of the LTC2140CUP-12 include 12-bit resolution, 25 Msps per-channel sample rate, two simultaneously sampled differential or single-ended inputs, a wide input bandwidth, and CMOS or DDR LVDS digital output modes programmable via either a parallel or simple serial interface. The integrated input common-mode buffer and optional digital output randomization further simplify high-performance signal-chain design. Technically, the part uses a multi-stage pipelined architecture with on-chip sample-and-hold, an internal voltage reference, and a digitally programmable gain. The 64-pin QFN package with exposed pad keeps the loop area compact, which is critical at 25 Msps where clock and input edge rates sit near 100 ps. Programmable output modes and configurable full-scale range allow the ADC to interface directly to FPGAs, ASICs, or standard microcontrollers. Typical applications for the LTC2140CUP-12 include wireless base-station receiver IF digitizers, handheld signal analyzers, portable imaging systems, ultrasound front ends, and multi-carrier software-defined radio (SDR) platforms. The combination of low power consumption and dual channels makes it particularly attractive for portable and battery-powered test equipment requiring two synchronized acquisition paths. When designing with this ADC, pay close attention to analog input network layout, decoupling of the internal reference, and the length-matched output routing for DDR LVDS modes. Operating modes are configured through either a parallel CMOS or a simple SPI-style serial interface, allowing all available modes—including output format, gain, and channel selection—to be programmed in-system. This page synthesizes distributor pricing, drop-in alternatives, parameter-by-parameter comparisons, and practical PCB-level design notes not found in the manufacturer datasheet alone.
LTC2140IUP-14 - 14-Bit 25Msps Dual ADC | Analog Devices | 64-QFN
The Analog Devices LTC2140IUP-14 is a 14-bit, 25 Msps low-power dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-lead QFN (9x9 mm) package with exposed pad. It integrates two matched ADC channels, each achieving ±1 LSB INL (typical) and ±0.3 LSB DNL (typical) with no missing codes over temperature, plus 1.2 LSBRMS transition noise for clean dynamic range. A pipelined ADC is a high-speed converter architecture that resolves one or two bits per internal stage and combines a sample-and-hold front end with multi-stage switched-capacitor gain/flash blocks; it is the workhorse architecture for communications baseband, ultrasound beamforming, and digital oscilloscope digitizers where multi-Msps rates are required. The LTC2140 sits in the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Compared with successive-approximation (SAR) ADCs, pipelined parts deliver far higher sample rates at the cost of pipeline latency, while still offering multi-bit-per-stage quantization. Key features include a flexible digital output interface supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS modes, and a separate output supply rail that lets the CMOS swing range from 0.4V to 1.8V independent of the analog 1.8V core. Programmable operating modes are accessible through either a parallel interface or a more flexible serial interface. The two channels sample simultaneously, which is essential for I/Q demodulators, phased-array receivers, and multi-channel data acquisition systems. Typical applications span communications infrastructure (IF/RF digitizers, diversity receivers, multi-antenna baseband), portable and battery-powered imaging, medical ultrasound front ends, industrial inspection cameras, and handheld or bench-top test instrumentation. Two matching channels let the part replace a dual-board ADC+amplifier chain in space-constrained designs. When designing with this part, allocate adequate copper area to the exposed pad for thermal relief (the dual 25 Msps core dissipates non-trivial power at full rate), route the LVDS/CMOS outputs with controlled impedance, and decouple OVDD and AVDD separately. The serial programming interface is recommended when the full feature set (output mode, gain, channel calibration) is required. This page synthesizes distributor stock and pricing, drop-in and same-package alternatives, and practical design notes that are not duplicated on the Analog Devices datasheet.
LTC2141CUP-14 - 14-Bit 40Msps Dual ADC, 64-QFN | Analog Devices
The Analog Devices LTC2141CUP-14 is a 14-bit, 40 Msps low-power dual analog-to-digital converter (ADC) housed in a 64-lead QFN (UP) package measuring 9x9 mm. Each ADC channel features ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over the operating temperature range, and 1.2 LSB RMS transition noise, providing true 14-bit linearity for demanding signal-chain designs. A separate output power supply allows the CMOS output swing to range from 1.2 V to 1.8 V, simplifying interface to modern FPGAs and ASICs. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a specified sampling rate. Dual ADCs integrate two synchronized sample-and-hold front ends and two pipelined conversion cores on a single die, enabling simultaneous sampling of two analog channels with matched gain, offset, and aperture delay. They sit within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. The pipelined architecture used in the LTC2141-14 family balances high sample rate (tens to hundreds of Msps) with low power consumption, making it the dominant choice for communications, imaging, and instrumentation front ends. Key features of the LTC2141CUP-14 include a choice of full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS digital outputs for trade-offs between pin count, board area, and EMI immunity. The device supports both differential and single-ended analog inputs, accepts parallel or serial programming through a simple SPI-like interface, and operates from a single 1.8 V supply. Low power consumption and excellent AC performance (high SNR and SFDR) make it equally suitable for portable, multi-channel data acquisition systems and for dense baseband capture in communications infrastructure. Typical applications include multi-channel communications receivers, portable and battery-powered instrumentation, medical imaging front ends, radar signal processing, and general-purpose high-speed data acquisition. When designing with this part, observe the recommended input common-mode voltage and drive the analog inputs through a wideband transformer or low-noise op-amp driver to preserve SFDR; insufficient analog input bandwidth is the most common root cause of degraded ENOB in pipelined ADC designs.
LTC2141IUP-12 - 12-Bit 40Msps Dual ADC | Analog Devices | 64-QFN
The Analog Devices LTC2141IUP-12 is a 12-bit, 40 Msps, low-power dual-channel pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) exposed-pad package with an industrial -40C to +85C operating temperature range (the "IUP" suffix designates industrial grade). Each of its two simultaneously sampling ADCs features a 12-bit resolution and is designed to digitize high-frequency, wide-dynamic-range signals with excellent spurious-free dynamic range. The device accepts differential or single-ended analog inputs and includes internal references plus an option for an external reference, allowing designers to trade off input range, noise and DC accuracy per channel. According to the manufacturer product page, the LTC2141-12 family lists at a 1ku starting price of $18.78 per part. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture that digitizes analog signals by dividing the conversion into multiple low-resolution stages, each driving a flash sub-ADC and a residue that is amplified and passed to the next stage. The pipelined topology sits within the broader hierarchy of data converters (ADC -> Nyquist ADC -> pipelined ADC -> mixed-signal IC) and is the dominant choice for sample rates from roughly 5 Msps to 200 Msps where both high throughput and low power are required - for example in wireless baseband, medical imaging and defense signal-intelligence receivers. Because the LTC2141-12 contains two matched ADCs sharing one clock, it doubles the channel density of a single 64-QFN footprint relative to two discrete single-channel parts. Key features of the LTC2141IUP-12 include 12-bit resolution, 40 Msps sampling rate, two simultaneously sampled differential input channels, selectable internal/external reference, low power dissipation for the speed class, CMOS-compatible outputs, and an exposed thermal pad that provides a low-theta-JA path for the heat generated by the two converters. The pipelined architecture calibrates its sub-ADC inter-stage gain and offset on-chip, eliminating user calibration and reducing time-to-design. The wide input bandwidth supports undersampling of IF signals, which makes the device attractive in communications receivers that digitize an IF directly rather than first down-converting to baseband. Architecturally, the LTC2141IUP-12 uses a multi-stage switched-capacitor pipeline per channel with proprietary linearization that minimizes integral non-linearity (INL) and differential non-linearity (DNL) at the 12-bit level. Each channel integrates its own sample-and-hold, ensuring matched timing between the two ADCs at the same applied clock edge, which is essential for I/Q demodulation and any diversity or beamforming receiver where the phase relationship between channels must be preserved. The 64-QFN (9x9) exposed-pad package also acts as the primary thermal relief path; PCB design must solder the EP to a continuous ground copper pour to achieve the rated thermal performance. Typical applications for the LTC2141IUP-12 include multi-carrier cellular base-station receivers, software-defined radio (SDR) front-ends, portable instrumentation and oscilloscopes, medical ultrasound beamformers, and industrial non-contact measurement. Industrial-grade temperature range and dual-channel density make it a strong fit when board area and power budget are tightly constrained and two matched channels are needed. When designing with the LTC2141IUP-12, place the part on a continuous ground plane with the exposed pad soldered to multiple thermal vias; this gives the lowest junction-to-ambient thermal resistance. Use short, matched-length differential traces for the analog inputs and keep the analog and digital return currents separated to avoid coupling digital switching noise into the analog front end. Decouple each supply pin with a 0.1uF ceramic capacitor placed as close as possible to the pin, with a bulk 10uF ceramic or tantalum capacitor nearby. This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical design notes not found in the manufacturer datasheet alone.