Transceptores Ethernet
Productos (3)
DP83TG720S-Q1 - 1000BASE-T1 Automotive Ethernet PHY | TI
The Texas Instruments DP83TG720S-Q1 is an AEC-Q100 qualified 1000BASE-T1 automotive Ethernet physical layer transceiver transmitting PAM3 ternary symbols at 750-MBd over a single unshielded or shielded twisted-pair cable, with RGMII and SGMII MAC interface support in a 36-pin VQFN (6x6 mm) wettable-flank package. An Ethernet PHY (physical layer transceiver) is the IC that converts digital MAC frames into analog signals suitable for transmission over a cable medium, sitting at the lowest layer of the OSI network hierarchy: PHY -> media access controller (MAC) -> Ethernet switch -> in-vehicle network. In automotive systems, single-pair Ethernet (SPE) as defined by IEEE 802.3bp (1000BASE-T1) and the Open Alliance spec reduces wiring weight and cost compared to four-pair 1000BASE-T. Key features include full xMII flexibility (RGMII and SGMII), compliance to IEEE 802.3bp and Open Alliance EMC and interconnect standards, and operation over unshielded or shielded single twisted-pair cable. The wettable-flank VQFN package supports optical inspection of solder joints required in automotive assembly lines, and the Q1 designation confirms AEC-Q100 automotive qualification. The DP83TG720S-Q1 transmits PAM3 ternary symbols at 750-MBd, encoding 1000 Mbps of payload onto a lower symbol rate to relax channel bandwidth requirements over automotive cabling. Per TI datasheet and the TI ti-ethernet-software repository, mainline Linux and TI RTOS drivers (dp83tg720.c) are available, easing integration with Zynq UltraScale+ and other MAC platforms. Typical applications include ADAS camera and radar backbone links, infotainment networks, domain and zonal gateways, and Power over Data Lines (PoDL) automotive designs - TI's PoDL reference design pairs this PHY with the DP83TC812S-Q1 for switchable 100/1000 Mbps operation. Design consideration: verify Open Alliance EMC compliance of your magnetics and common-mode choke selection, and confirm MDIO post-reset stabilization timing (T6.2) before first MDIO access. This page synthesizes verified datasheet data, drop-in family alternatives, application pairings, and design notes not found in the manufacturer datasheet. Pricing as of 2026-10-16.
KSZ8001LI-TR - 10/100 PHY Transceiver, MII/RMII/SMII | Microchip
The Microchip Technology KSZ8001LI-TR is a single-chip 10BASE-T/100BASE-TX/100BASE-FX physical layer transceiver that supports MII, RMII, and SMII host interfaces, housed in a 48-pin LQFP (7x7 mm) package with industrial -40C to +85C operating range. It integrates 3.3V single-supply operation, LinkMD cable diagnostics with up to 200m cable length measurement and ±2m accuracy, and robust 130m+ cable operation, making it a versatile Ethernet PHY for embedded designs. What is an Ethernet PHY transceiver? A Physical Layer device (PHY) is the analog front-end of an Ethernet link, sitting between the digital MAC controller and the magnetic transformer/RJ-45 connector. The PHY handles line coding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), clock/data recovery, adaptive equalization, and link-pulse detection. The KSZ8001LI-TR belongs to the Fast Ethernet (100 Mbps) PHY family, which falls under Interface ICs -> Network Interface -> Ethernet Transceiver in the broader semiconductor hierarchy. Key differentiating features include LinkMD TDR-based cable diagnostics that detect open/short conditions and report cable length up to 200m with ±2m accuracy, robust operation over standard Cat-5 cables up to 130m+, HP Auto-MDIX support for automatic crossover detection, and flexible MII/RMII/SMII host bus selection that lets the same PHY connect to MACs with different pin-count constraints. The device supports both copper (100BASE-TX, 10BASE-T) and fiber (100BASE-FX) media via an external fiber transceiver. The KSZ8001LI-TR architecture uses a 3.3V analog supply plus a 1.8V digital core derived from an internal LDO, with separate VDDIO rails supporting 3.3V or 2.5V MAC interface voltages. Typical power consumption is 172 mW. The PHY connects to a MAC via parallel MII (18 pins), reduced MII (RMII, ~9 pins), or serial MII (SMII, 4 pins), configured at reset via strap pins. Auto-negotiation follows IEEE 802.3u Clause 28. Typical applications include industrial Ethernet IP cameras, factory automation PLCs, networked printers, set-top box Ethernet ports, embedded IoT gateways with wired connectivity, and any embedded system requiring a small-footprint 10/100 Ethernet PHY with diagnostic capability. The LinkMD feature is particularly valuable in managed switches and remote installations where cable fault localization reduces service calls. Design considerations include providing a 25 MHz reference clock (or 50 MHz for RMII), placing the device within 25 mm of the magnetic transformer, implementing proper 50 ohm differential routing for the MDI traces, and supplying adequate decoupling (0.1 uF plus 10 uF bulk) on each supply rail. The KSZ8001LI-TR differs from the -L variant (KSZ8001L) by offering higher-grade industrial temperature support and the -TR suffix denotes Tape and Reel packaging. This page synthesizes distributor pricing as of 2026-10-16, real drop-in alternatives sourced from cross-reference databases, and practical engineering considerations to accelerate Ethernet PHY selection beyond the bare manufacturer datasheet.
KSZ9031RNXIA - Gigabit Ethernet PHY Transceiver RGMII | Microchip
The Microchip Technology KSZ9031RNXIA is a fully integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Gigabit Ethernet physical-layer transceiver that supports 1.8V, 2.5V, and 3.3V I/O voltages with RGMII MAC interface, housed in a 48-pin QFN (7x7 mm) package with industrial temperature grade (-40C to +85C). The device provides a complete 10/100/1000 Mbps Ethernet PHY solution for transmission and reception over standard CAT-5 unshielded twisted pair (UTP) cable. An Ethernet PHY (Physical Layer transceiver) is a critical mixed-signal IC that sits between the digital MAC (Media Access Controller) in a processor/switch and the analog copper cable. PHY transceivers handle line coding (PAM-3/PAM-5 for 1000BASE-T), echo cancellation, crosstalk mitigation, and link training; they sit below the MAC in the OSI model hierarchy: PHY -> transceiver -> network interface -> wired connectivity IC. The KSZ9031 family occupies the Gigabit Ethernet PHY category within Power-over-Ethernet-aware wired networking semiconductors. Key features include Wake-on-LAN support, LinkMD cable diagnostics for cable plant fault detection, Auto-MDI/MDIX crossover, jumbo frame support up to 9.6 KB, and an integrated 1.2V LDO regulator. The RGMII interface supports 1.5V/1.8V/2.5V/3.3V HSTL, SSTL, or LVCMOS signaling to a wide range of MACs, FPGAs, and Ethernet switches. Energy-detect power-down and EEE (Energy Efficient Ethernet) further reduce system power consumption during idle link states. The KSZ9031 uses DSP-based echo and crosstalk mitigation, on-chip termination resistors, and adaptive equalization to deliver robust 1000BASE-T performance over marginal cable plants. The device provides two LED outputs, an MDIO management interface, and requires only a single 25 MHz reference clock. Typical applications include industrial Ethernet switches, factory automation controllers, automotive infotainment/networking, IP cameras and surveillance, network printers, and any embedded system requiring 10/100/1000 Mbps copper Ethernet connectivity with RGMII host interface. The KSZ9031 is AEC-Q100 qualified for automotive use. When designing with this device, provide a clean analog supply (AVDDH 3.3V) and digital supply decoupling per the datasheet reference circuit; place the 48-pin QFN thermal/exposed pad onto a proper ground-solder land with multiple thermal vias for reliable operation. Use the MDIO/MDC pins for PHY management and configuration. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.