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Productos (32725)

TXS0108ERGYR - 8-Bit Bidirectional Level Shifter | Texas Instruments
TXS0108ERGYR

TXS0108ERGYR - 8-Bit Bidirectional Level Shifter | Texas Instruments

The Texas Instruments TXS0108ERGYR is an 8-bit bidirectional voltage-level translator designed for open-drain and push-pull applications. It operates with a VCCA range of 1.4V to 3.6V and a VCCB range of 1.65V to 5.5V (with VCCA <= VCCB), supporting maximum data rates of 110Mbps for push-pull signals and 1.2Mbps for open-drain buses. The device comes in a 20-pin VQFN (RGY) package measuring 3.5x4.5mm with an operating temperature range of -40C to +85C. A voltage-level translator, also called a level shifter, is a logic IC that enables communication between devices operating at different supply voltages, such as a 1.8V microcontroller interfacing with a 5V peripheral. Level translators sit within the broader logic IC family and are essential in any mixed-voltage embedded system. The TXS0108E requires no direction-control signal because its auto-direction sensing architecture detects data flow automatically, reducing MCU pin usage and firmware complexity. Key features include VCC isolation, which places all outputs in high-impedance if either supply is at GND; no power-supply sequencing requirement, since either VCCA or VCCB can ramp first; and a one-shot edge-rate accelerator that boosts rise times to achieve the 110Mbps push-pull data rate. The transistor-based pass-gate architecture supports both open-drain buses such as I2C and push-pull interfaces such as SPI and UART without configuration. Typical applications include I2C, SPI, and UART level shifting between low-voltage MCUs (1.8V/2.5V/3.3V) and 5V peripherals, SD card and SIM card interfaces, and general-purpose GPIO translation in industrial and consumer systems. As of 2026-08-30, pricing starts at approximately $0.60-$0.90 at 1-piece quantity from authorized distributors. Design tip: always keep VCCA <= VCCB, place 0.1uF and 10uF decoupling capacitors close to both supply pins, and use external pull-up resistors on both sides for open-drain operation.

USD $0,40 En stock
UCS-NVES1T9K1V - 1.9TB E1.S NVMe Gen4 SSD | Cisco
UCS-NVES1T9K1V

UCS-NVES1T9K1V - 1.9TB E1.S NVMe Gen4 SSD | Cisco

The Cisco UCS-NVES1T9K1V is a 1.90 TB enterprise NVMe solid state drive in an E1.S (15 mm) form factor, built on the Kioxia XD7P high-performance, mid-endurance flash platform with a PCI Express NVMe 4.0 (x1) host interface for Cisco UCS servers. The equivalent commercial SKU is CAI-NVES1T9K1V, listed by distributors as the Cisco 1.9TB E1.S 15mm Kioxia XD7P High Performance Mid Endurance Gen4 1x NVMe drive. An enterprise NVMe SSD is a solid state storage device that connects directly to the PCIe bus using the NVMe protocol, bypassing SATA/SAS controller bottlenecks to achieve lower latency and higher IOPS. Within the storage hierarchy, it sits as block storage below the server OS layer and above the raw NAND media; the E1.S (EDSFF) form factor is the compact successor to M.2 and U.2 drives, optimized for dense 1U/2U rack servers. Cisco qualifies specific drive PIDs for its UCS C-Series rack servers so that firmware, thermal profiles, and drive-slot mapping are fully supported under Cisco TAC. Key characteristics of this drive include its 1.90 TB raw capacity, PCIe 4.0 NVMe x1 electrical interface, E1.S 15 mm mechanical format with an integrated drive carrier for UCS drive slots, and Kioxia XD7P NAND tuned for high performance with mid endurance - a fit for read/write-mixed enterprise workloads rather than extreme write-intensive caching. Cisco lists the supported host platform as the UCS C845A M8 AI Server, an NVIDIA MGX-based accelerated computing system. In deployment, the UCS-NVES1T9K1V typically serves as local high-performance boot or data storage for AI training nodes, database servers, and virtualization hosts where NVMe Gen4 bandwidth reduces data loading time. Cisco validates drive-to-server interoperability through the UCS Hardware Compatibility List (HCL), so mixing unqualified third-party E1.S drives can void hardware support. Design consideration: verify the target UCS server chassis and firmware release support E1.S Gen4 x1 drives via the Cisco UCS HCL before ordering, and note that the drive reaches Cisco end of sale on 2026-12-25, so long-term spares should be procured before that date. This page synthesizes distributor pricing, lifecycle dates, platform compatibility, and procurement guidance for both the UCS-NVES1T9K1V and CAI-NVES1T9K1V SKUs in one place - information typically spread across Cisco, Ingram Micro, CDW, and lifecycle-tracking sources.

USD $3.550,00 En stock
UCS-NVES3T8K1V - Cisco 3.8TB NVMe E1.S SSD | Cisco | UCS Servers
UCS-NVES3T8K1V

UCS-NVES3T8K1V - Cisco 3.8TB NVMe E1.S SSD | Cisco | UCS Servers

The Cisco UCS-NVES3T8K1V is a 3.8TB PCI Express 4.0 (PCIe NVMe 4.0) E1.S (15 mm) internal solid state drive based on the Kioxia XD7P high-performance, medium-endurance SSD series, designed for Cisco UCS C-Series rack servers, including the UCS C845A M8 AI server. The drive connects through a x4 PCIe 4.0 NVMe interface and is qualified by Cisco as a server storage module within the UCS C-Series ecosystem. An NVMe SSD (Non-Volatile Memory Express solid state drive) is a storage device that attaches directly to the PCIe bus rather than through legacy SATA/SAS controller paths. In the storage hierarchy, it sits at the top of the enterprise flash tier: NAND flash -> SSD controller -> NVMe protocol -> PCIe transport -> server platform. By eliminating the SAS/SATA translation layer, NVMe reduces latency and increases queue depth, which is why data center and AI workloads increasingly standardize on NVMe drives such as this one. Key characteristics of the UCS-NVES3T8K1V include its 3.80 TB usable capacity, its compact E1.S 15 mm edge-connector form factor (part of the EDSFF family standardized for dense server platforms), and its PCIe NVMe 4.0 host interface. The underlying Kioxia XD7P silicon is positioned as high performance with medium endurance (drive writes per day rating [DATA_NEEDED: DWPD]), targeting read-intensive and mixed enterprise workloads rather than extreme write-cycle caching tiers. The XD7P platform uses enterprise-grade NAND and a controller tuned for consistent low latency, making the drive suitable as boot, scratch, or high-IOPS data storage. Because it is a Cisco-qualified PID, firmware and thermal behavior are validated against UCS C-Series chassis airflow and power profiles, which third-party drives cannot guarantee. Typical applications include AI/ML training data pipelines on the UCS C845A M8, virtualization and database storage tiers, high-density composable infrastructure, and general rack-server storage expansion where a 3.8TB E1.S NVMe module is required. A key design consideration: this PID is schedule-based for end of sale - Cisco has announced end of sale for UCS-NVES3T8K1V= on 2026-12-25 - so new designs should verify lifecycle status and plan spares accordingly. This page synthesizes distributor pricing, lifecycle information, and drop-in family alternatives not consolidated on the manufacturer datasheet page.

USD $4.590,00 En stock
UDA1341TS/N1 - Stereo Audio CODEC, SSOP-28 | NXP Semiconductors
UDA1341TS/N1

UDA1341TS/N1 - Stereo Audio CODEC, SSOP-28 | NXP Semiconductors

The NXP Semiconductors UDA1341TS/N1 is a single-chip stereo audio CODEC combining a 4-channel Analog-to-Digital Converter and a 2-channel Digital-to-Analog Converter using bitstream conversion techniques, housed in a 28-pin SSOP (SOT341-1) package. It features 20-bit ADC/DAC resolution, integrated Programmable Gain Amplifiers (PGA), digital Automatic Gain Control (AGC), and an L3-interface for microcontroller control of audio processing features including de-emphasis, volume, bass boost, treble, and soft mute. An audio CODEC (Coder-Decoder) is a mixed-signal integrated circuit that converts analog audio signals into digital form for processing or storage, and converts digital audio back into analog for playback. CODECs sit at the boundary between the analog and digital audio domains, and are foundational components in the audio signal chain: microphone input -> analog PGA -> ADC -> digital audio bus -> DAC -> analog output -> speakers/headphones. The UDA1341TS belongs to NXP's economy audio CODEC family, designed for cost-sensitive MiniDisc (MD), home stereo, and portable applications. Key features include 4 analog input channels and 2 analog output channels, support for multiple digital audio data formats (I2S-bus, LSB-justified, MSB-justified), a fully integrated analog front end, on-chip DSP features in playback mode, and partial pin compatibility with the UDA1340M and UDA1344TS for easy PCB upgrades. The device operates over -20C to +85C ambient temperature range typical of consumer audio equipment. The UDA1341TS architecture uses oversampling bitstream (sigma-delta) conversion to achieve 20-bit resolution with high noise immunity and reduced analog filtering requirements. The integrated PGA and AGC simplify external analog circuitry, while the L3-interface allows software control of digital audio features without external DSP hardware. This makes the UDA1341TS suitable for compact, low-cost audio designs. Typical applications include MiniDisc (MD) recorders and players, home stereo receivers and CD recorders, portable digital audio devices, set-top boxes, and automotive head units. The wide input channel count supports multi-source mixing for recording applications. When designing with the UDA1341TS, pay careful attention to power supply decoupling and grounding to avoid digital switching noise coupling into the analog sections, since the CODEC integrates both sensitive analog and high-speed digital functions on the same die. Use separate analog and digital supply pins as recommended in the datasheet, with low-impedance ground returns. This page synthesizes current NXP datasheet specifications, real distributor pricing, drop-in alternative CODECs, and practical analog/digital design guidance not found in the manufacturer datasheet alone.

USD $3,05 En stock
UJA1018TK - LIN System Basis Chip w/ LED Drivers | NXP
UJA1018TK

UJA1018TK - LIN System Basis Chip w/ LED Drivers | NXP

The NXP UJA1018TK is a LIN 2.0/2.0A/2.1/2.2/SAE J2602 system basis chip (SBC) with integrated low-drop voltage regulator and LED drivers, housed in a 16-terminal HVSON (3.5x5.5 mm) exposed-pad package. It combines a single LIN-bus transceiver, a 5.0 V/70 mA LDO regulator, and dedicated LED driver outputs that simplify compact mechatronic and automotive body-electronic node designs. A LIN system basis chip is a class of mixed-signal interface IC that integrates a bus transceiver with on-chip power management and support peripherals. By collapsing the transceiver, voltage regulator, and actuator drivers into a single die, an SBC reduces PCB area, lowers quiescent current, and provides a robust EMC/ESD front end for in-vehicle networks governed by the LIN/J2602 family of standards. The UJA1018TK sits within the automotive networking segment alongside CAN and FlexRay transceivers, and is commonly used as a body-control sub-node tying switches, sensors, and LEDs back to a central body control module. Key features of the UJA1018TK include compliance with LIN 2.0/2.1/2.2 and SAE J2602, integrated 5.0 V low-drop regulator capable of delivering up to 70 mA to external loads, programmable LIN-bus slew rate for EMC control, and dedicated LED driver pins capable of sourcing the current required for indicator or status lamps. The device supports node-position identification through a daisy-chained LIN-switch path, allowing cost-effective address assignment in multi-node LIN chains. The architecture combines a high-voltage analog front end tolerant of automotive 12 V transients with a low-power digital LIN protocol state machine. An integrated LIN bus switch enables address assignment without external EEPROM, while thermal shutdown, load-dump protection, and an exposed thermal pad enable AEC-Q100-style automotive operation across the -40C to +150C automotive temperature range. Supply current is typically around 4.5 mA in active mode, supporting always-on body networks. Typical applications include automotive door modules, seat controllers, steering-column switches, sunroof and mirror modules, climate-control panels, and any LIN-attached mechatronic node that also needs to drive LEDs. Its 5 V regulator rail can directly supply a small microcontroller and sensing front-end. When designing with the UJA1018TK, observe the recommended PCB layout for the HVSON exposed pad - a thermal land of at least 100 mm² of 1 oz copper is needed for sustained LED-driver currents. Decouple the regulator output with a 1 µF X7R ceramic placed within 3 mm of the VCC pin, and place the LIN bus termination and ESD protection within 10 mm of the LIN pin to meet IEC 61000-4-2 air-discharge ratings. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical PCB/EMC design notes not found in the manufacturer datasheet.

USD $1,65 En stock
UJA1018TK,118 - LIN 2.x SBC with 5V LDO & LED Drivers | NXP
UJA1018TK,118

UJA1018TK,118 - LIN 2.x SBC with 5V LDO & LED Drivers | NXP

NXP UJA1018TK,118 is a LIN 2.0/2.1/2.2 and SAE J2602 compliant system-basis chip (SBC) integrating a LIN transceiver, a 5 V low-dropout (LDO) voltage regulator rated up to 70 mA, and two LED drivers, housed in a 16-pin HVSON (3.5 x 5.5 mm) exposed-pad package. A LIN System Basis Chip (SBC) is a mixed-signal IC that combines the physical-layer transceiver, an internal supply for the local microcontroller, and bus-switching or indicator-driving peripherals in a single die. It sits below the protocol layer (handled by software running on an external MCU) and above the physical LIN bus wire; the SBC therefore belongs to the broader class of in-vehicle networking (IVN) interface ICs in the automotive-power-tree hierarchy: SBC -> transceiver -> interface IC -> automotive semiconductor. Key features include LIN 2.0/2.1/2.2/SAE J2602 compliance, downward compatibility with LIN 1.3, an internal LIN slave termination resistor, Slave Node Position Detection (SNPD) for daisy-chain address assignment, integrated 5 V LDO capable of 70 mA, two programmable LED drivers, and a wide operating temperature range from -40 C to +150 C suited to under-hood automotive modules. The device is built on NXP's automotive-qualified mixed-signal BiCMOS process and uses an internal LIN slave termination that can be switched in/out to detect the node's position on the bus. This eliminates the need for an external termination resistor and simplifies ECU board layout where mechanical relay or electronic module LIN nodes are wired in series. Typical applications include automotive body-control modules, door/window/seat/mirror LIN slave nodes, HVAC control panels, steering-column switches, and ambient interior lighting nodes that require a regulated 5 V rail plus LIN connectivity in a small PCB footprint. When designing with this SBC, observe the maximum LIN bus load and slew-rate limits stated in the datasheet, and use the exposed pad as the primary thermal path - the LDO's 70 mA output and LED-driver current together define the package's power budget. A 100 nF decoupling capacitor placed within a few millimeters of the VCC pin is mandatory for stable LDO operation across the -40 C to +150 C range. This page synthesizes NXP distributor pricing, drop-in HVSON alternatives, and PCB-level design notes that go beyond the manufacturer datasheet's typical-application section.

USD $1,55 En stock
UJA1023T - LIN 2.0 I/O Slave, 16-SO, NXP
UJA1023T

UJA1023T - LIN 2.0 I/O Slave, 16-SO, NXP

The NXP UJA1023T is a stand-alone Local Interconnect Network (LIN) 2.0 compliant I/O slave integrated circuit, designed to replace discrete input and output handling components inside automotive electronic control units. The device integrates a LIN 2.0 controller, an integrated LIN transceiver (LIN 2.0 / SAE J2602 compliant, LIN 1.3 compatible), a 30 kΩ slave termination resistor, and eight general-purpose I/O lines, all packaged in a 16-pin Small Outline (SOT109-1 / 16-SO) surface-mount outline. A LIN transceiver IC is a category of in-vehicle networking transceivers that serves as the physical-layer interface between a microcontroller's UART and the single-wire LIN bus. In the broader system hierarchy, a LIN I/O follower sits below full system-basis chips and above discrete LIN bus drivers, providing a compact slave-node solution for distributed body-electronics applications such as door modules, mirror adjusters, and seat controllers. Key functional features of the UJA1023T include LIN 2.0 / SAE J2602 compliance for the physical layer, LIN 1.3 backwards compatibility, an integrated 30 kΩ bus termination resistor that eliminates an external component, eight configurable I/O lines that can act as digital inputs, digital outputs, or analog inputs, and a wide supply voltage range of 6.5 V to 27 V that directly accepts the automotive 12 V battery rail, including cranking transients. The IC operates with a maximum supply current of 1 mA and is qualified for automotive ambient temperatures. Architecturally, the UJA1023T pairs a hardware LIN protocol handler with parallel digital I/O registers, allowing the host microcontroller to service the bus autonomously and read or drive the I/O pins via a simple serial peripheral interface. Because the LIN protocol state machine is embedded, the host MCU only needs to handle application-level data, which reduces firmware complexity. Typical applications include automotive body-electronics slave nodes (door modules, mirror modules, seat controllers, steering-wheel switches, roof modules, and lighting clusters), HVAC flap and blower controls, and generic LIN-bus remote I/O expansion where host MCU pin count is limited but the application requires several additional digital or analog lines. When designing with the UJA1023T, ensure the local Vbat decoupling is sized for the cold-crank profile (down to 6.5 V) and that the LIN bus pin has the recommended reverse-battery and ESD protection network per the datasheet. Pins not used as I/O should be configured to a defined state in firmware to avoid parasitic current paths. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

USD $1,98 En stock
UJA1023T/2R04/C,51 - LIN 2.0 I/O Slave | NXP Semiconductors
UJA1023T-2R04-C51

UJA1023T/2R04/C,51 - LIN 2.0 I/O Slave | NXP Semiconductors

The NXP Semiconductors UJA1023T/2R04/C,51 is a stand-alone Local Interconnect Network (LIN) I/O follower (slave) that integrates a LIN 2.0 controller, a LIN 2.0/SAE J2602-compliant transceiver, a 30 kOhm LIN-slave termination resistor, and eight configurable I/O ports into a single 16-pin SOIC package supplied from 6.5 V to 27 V. It is designed to replace the discrete components commonly used in electronic control units (ECUs) for digital input capture, digital output driving, and LIN-bus communication. What is a LIN I/O follower? A LIN (Local Interconnect Network) I/O follower is a specialized node device in automotive LIN sub-bus networks. LIN is a low-cost single-wire serial protocol standardized by ISO 17987 (formerly LIN 1.3 / LIN 2.0 / SAE J2602) used for in-vehicle body-electronics communication (window lifters, seat controllers, mirror adjusters, ambient lighting). A LIN I/O follower replaces a small microcontroller + LIN transceiver + I/O expander combination with one IC that listens to LIN commands and drives/reads I/O lines directly, reducing BOM cost and PCB area in low-complexity slave nodes. Key features include LIN 2.0 protocol compliance with LIN 1.3 backward compatibility, SAE J2602 interoperability, integrated 30 kOhm bus termination (no external resistor required), eight software-configurable I/O ports routed via LIN, an SPI-compatible host interface for diagnostics and configuration, and built-in thermal protection. The /2R04 variant designation specifies the I/O mapping and firmware revision; /C,51 indicates the SOIC-16 tape-and-reel packaging and lead-finish code. Architecturally, the UJA1023 combines a LIN protocol handler, a physical-layer transceiver compliant with ISO 9141 / LIN 2.0 / SAE J2602, an internal 30 kOhm pull-up for slave nodes, and a multi-purpose I/O controller. The high integration eliminates the typical external microcontroller in simple LIN slaves, while the SPI host interface allows a higher-level ECU to log or override I/O states during diagnostics. Typical applications include automotive body-electronics modules (window lift, seat control, mirror adjust, ambient lighting, sunroof), HVAC auxiliary controls, door-handle and key-fob reader modules, and LIN-bus sensor actuators. The wide 6.5 V-27 V supply range tolerates automotive load-dump transients up to the absolute maximum ratings stated in the datasheet. Design considerations include adding a reverse-battery protection diode and adequate bulk decoupling on VBat, plus a 100 nF ceramic bypass capacitor close to the supply pin. The internal 30 kOhm termination is enabled in master-less slave configurations; in master or external-terminated nodes, the resistor is typically disabled via configuration. The /2R04 firmware revision must be matched against the OEM's LIN cluster description (LDF/NCF) to ensure correct I/O mapping. This page synthesizes verified distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

USD $1,95 En stock
UJA1169ATK/3Z - Mini HS-CAN SBC, 3.3V/250mA, AEC-Q100 | NXP
UJA1169ATK/3Z

UJA1169ATK/3Z - Mini HS-CAN SBC, 3.3V/250mA, AEC-Q100 | NXP

The NXP UJA1169ATK/3Z is a mini high-speed CAN System Basis Chip (SBC) in the UJA1169ATK family, integrating an ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver that supports CAN FD up to 5 Mbit/s together with an on-board 3.3 V (V1) LDO regulator rated at 250 mA for the host microcontroller supply, all housed in a 20-pin HVSON package (3.5 x 5.5 mm). What is a CAN System Basis Chip (SBC)? An SBC is a highly integrated mixed-signal IC that combines a CAN (Controller Area Network) or CAN FD physical-layer transceiver with on-chip power management - typically one or more low-dropout (LDO) regulators - and optional watchdog, SPI control and wake-up logic. In the automotive ECU hierarchy, an SBC sits between the 12 V board net, the host microcontroller, and the CAN bus, replacing several discrete components: an HS-CAN transceiver, a 5 V or 3.3 V regulator for the MCU, reverse-battery protection and bus ESD protection. The wider taxonomy is: SBC -> CAN transceiver -> automotive networking IC -> power management IC -> semiconductor. Key features of the UJA1169ATK/3Z include 250 mA continuous V1 current to power a small MCU, support for CAN FD at 5 Mbit/s, integrated bus dominant clamping and very low-current standby modes with remote wake-up via the bus. The transceiver meets the stringent automotive EMC and ESD requirements of the ISO 11898-2:2016 standard and the SAE J2284-1 to J2284-5 specifications, while the integrated regulator and protection circuitry reduce external component count and PCB area in ECU designs. Architecturally, the part uses a high-voltage analog/mixed-signal process for the bus-side drivers and a low-voltage digital block for the SPI register set and V1 LDO. This dual-rail approach allows direct connection to a 12 V automotive supply while still powering the host MCU from the on-chip 3.3 V regulator in the /3Z variant. Typical applications include body control modules, gateway ECUs, CAN node power management in 12 V systems, ADAS sensor interface nodes and any automotive system that needs a single-chip CAN interface plus local MCU supply. Compared with discrete CAN transceivers plus external regulators, the UJA116ATK family shrinks the BOM and simplifies EMC compliance. When designing with the UJA1169ATK/3Z, ensure the 12 V supply is properly filtered, route the CANH/CANL lines as a 120 ohm twisted pair, and decouple V1 with the value recommended in the manufacturer datasheet. The /3Z variant is the 3.3 V V1, tape-and-reel orderable variant; the 5 V variant is the UJA1169ATK/F/3Z and the non-Z variants differ only in packing or V1 voltage. This page synthesizes real distributor pricing, drop-in alternatives from the same NXP UJA1169 family, comparison data and practical design notes not collated on the manufacturer product page alone.

USD $2,10 En stock
UJA1169ATK/F/3 - Mini HS-CAN SBC, 3.3V LDO, 20-HVSON | NXP
UJA1169ATK/F/3

UJA1169ATK/F/3 - Mini HS-CAN SBC, 3.3V LDO, 20-HVSON | NXP

The NXP Semiconductors UJA1169ATK/F/3 is a mini high-speed CAN System Basis Chip (SBC) that integrates an ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver (supporting CAN FD up to 5 Mbit/s) together with a 3.3 V, 250 mA microcontroller supply and an internal 5 V regulator (V2) for the CAN transceiver. Housed in a 20-pin HVSON (3.5 x 5.5 mm) package, it provides partial networking with selective wake-up via CAN FD-passive capability. The /3 suffix designates the V1 regulator variant as 3.3 V rather than the 5 V used in the base UJA1169ATK, while the /F suffix enables the selective wake-up (partial networking) function. The device includes a watchdog, SPI control interface, and comprehensive protection features for automotive network nodes. A System Basis Chip (SBC) is an automotive-grade mixed-signal IC that consolidates a CAN/CAN FD transceiver with one or more voltage regulators, system protection, and optional wake-up logic into a single package. SBCs sit between the vehicle battery and the microcontroller, replacing several discrete components (transceiver, LDO, watchdog, reset generator) and reducing PCB area, BOM cost, and quiescent current in always-on networks. The UJA1169ATK family targets body-control modules, gateway ECUs, and zonal architectures in modern vehicles. Key features include a 3.3 V / 250 mA V1 regulator for the host MCU, a 5 V internal V2 regulator for the CAN transceiver, low quiescent current in standby and sleep modes with selective wake-up, an SPI interface for configuration and diagnosis, and integrated bus-failure management. The selective wake-up function allows ECUs to ignore CAN traffic not addressed to them, dramatically reducing network-wide quiescent current in CAN partial-networking architectures. The HVSON-20 package with exposed pad provides low thermal resistance for reliable operation in under-hood environments. The UJA1169ATK/F/3 is typically used in body and comfort ECUs, gateway modules, and any node that must wake selectively from CAN partial-networking traffic. It is particularly suited to OEM platforms targeting ISO 11898-2:2016 compliance with CAN FD-passive wake-up, where legacy nodes and FD-capable nodes coexist on the same bus. When designing with this SBC, ensure the HVSON exposed pad is soldered to a sufficient copper area for thermal dissipation, follow NXP's reference layout for the bus split termination, and configure the partial-networking filter mask in software to match the OEM-defined wake-up frame. All configuration is via SPI from the host MCU; no external programming is required. This page synthesizes distributor pricing, drop-in same-family variants, and practical design notes for the UJA1169ATK/F/3 that go beyond what the manufacturer datasheet alone provides.

USD $3,48 En stock
UJA1169ATK/F/3Z - Mini HS-CAN SBC with 3.3V LDO | NXP
UJA1169ATK/F/3Z

UJA1169ATK/F/3Z - Mini HS-CAN SBC with 3.3V LDO | NXP

The NXP UJA1169ATK/F/3Z is a mini high-speed CAN System Basis Chip (SBC) that integrates an ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver supporting CAN FD up to 5 Mbit/s, alongside an onboard 3.3 V microcontroller supply (V1) and a second 5 V onboard LDO (V2), both rated at 250 mA, in a 20-pin HVSON (3.5x5.5 mm) package with exposed thermal pad. An SBC is an integrated automotive network IC that combines a CAN (Controller Area Network) physical-layer transceiver with one or more voltage regulators and supporting features such as watchdog, wake-up management, and fail-safe output control. The SBC sits between the vehicle battery (VBAT) and the microcontroller, providing a regulated supply while the HS-CAN transceiver links the host MCU to the in-vehicle CAN bus. This class of device collapses what would otherwise be several discrete ICs into a single package, reducing PCB area, BOM cost, and quiescent-current budget in body, chassis, and powertrain ECUs. Key specifications of the UJA1169ATK/F/3Z include: 3.3 V V1 LDO with 250 mA current capability, 5 V V2 LDO at 250 mA for the internal transceiver and additional onboard hardware, CAN FD data rates up to 5 Mbit/s, very low VBAT quiescent current in standby modes, and integrated fail-safe behavior with a watchdog and SPI control. The /3 suffix on this variant fixes V1 at 3.3 V rather than the 5 V used in the UJA1169ATK, UJA1169ATK/F, UJA1169ATK/X, and UJA1169ATK/X/F members of the family. The /F suffix indicates the SPI-gated watchdog configuration; the trailing Z designates the 13-inch reel SBB packing format. Architecturally, the UJA1169ATK/F/3Z pairs a high-speed CAN physical layer with two linear regulators sharing a common thermal pad. The HVSON-20 exposed-pad package keeps thermal resistance low so both regulators can sustain full 250 mA loads simultaneously, while the integrated CAN transceiver implements the ISO 11898-2:2016 standard and supports the SAE J2284 series bit-timing benchmarks used by global automakers. The device supports selective wake-up and several low-power modes that allow an ECU to drop to microamp-level quiescent draw when the bus is idle. Typical automotive applications include body control modules, gateway ECUs, sensor cluster nodes, HVAC controllers, comfort and convenience modules, and small powertrain controllers. The 3.3 V LDO mapping of the /3 variant makes the device a direct fit for low-voltage host microcontrollers such as the NXP S32K1xx family that operate from a 3.3 V rail. When laying out the PCB, place decoupling capacitors directly at V1 and V2 with short, wide ground returns, and attach the exposed thermal pad to a copper plane sized for the worst-case dissipation. Use a 13-inch reel handling process consistent with the Z suffix to integrate this part into high-volume surface-mount lines. This page synthesizes distributor pricing, drop-in alternative selection, and practical SBC design notes not found in the manufacturer datasheet.

USD $2,31 En stock
UJA1169ATKZ - Mini HS-CAN SBC, 5V/3.3V LDO 250mA | NXP
UJA1169ATKZ

UJA1169ATKZ - Mini HS-CAN SBC, 5V/3.3V LDO 250mA | NXP

The NXP UJA1169ATKZ is a mini high-speed CAN System Basis Chip (SBC) integrating an ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver with CAN FD support up to 5 Mbit/s, plus an integrated 5 V or 3.3 V, 250 mA voltage regulator (V1) for a host microcontroller or peripheral loads, all housed in a 20-pin HVSON (3.5 x 5.5 mm) exposed-pad package. It targets compact automotive body and network applications where PCB area, BOM count, and quiescent current are critical, and where a clean CAN bus interface plus a small, protected supply rail must coexist with a serial peripheral interface (SPI) control channel and independent watchdog. A System Basis Chip (SBC) is a category of automotive networking IC that combines a physical-layer transceiver with on-chip power, supervision, and diagnostic functions into a single die. Within the broader hierarchy, SBCs sit between standalone CAN transceivers (which provide only the bus interface) and full ECU power-management companions (PMICs), allowing one part to replace what traditionally required three or four discrete devices. The UJA1169 family achieves this by merging an HS-CAN physical layer with a low-drop linear regulator, a watchdog, an SPI configuration port, and a LIMP output for fail-safe system behavior. Key features include CAN FD support up to 5 Mbit/s for modern in-vehicle networking bandwidth, integrated 250 mA LDO selectable between 3.3 V and 5 V to host an MCU without an external regulator, very low quiescent current in standby modes for permanently connected nodes, integrated watchdog with window or timeout behavior, SPI for control and status, and a LIMP pin for graceful system degradation. The HVSON-20 exposed pad provides a low thermal resistance path suitable for harsh automotive environments. Architecturally, the device uses a mixed-signal BiCMOS process: the CAN transceiver meets ISO 11898-2:2016 (and the upcoming merged ISO 11898-2/5/6 standard for selective wake-up and CAN FD), while the regulator is implemented as a high-side series pass element with reverse-polarity and load-dump protection suitable for 12 V automotive battery rails. Battery/supply voltage can reach 28 V (with load-dump transient tolerance typical for 12 V systems). Typical applications include automotive body control modules (BCMs), gateway and CAN nodes requiring a regulated MCU rail, network sensors and actuators, HVAC controllers, seat/door/zone modules, and anywhere an HS-CAN node with integrated microcontroller power is needed to shrink the BOM. When designing with this part, derate the 250 mA regulator headroom against the V1 voltage tolerance, since a 12 V battery input powering a 5 V, 200 mA MCU load dissipates roughly 1.4 W in the package. Sufficient copper area on the exposed pad is recommended to keep the junction within the automotive temperature range. This page synthesizes NXP distributor pricing, qualified drop-in alternative cross-references, and practical automotive-node design notes that go beyond the manufacturer datasheet itself.

USD $1,72 En stock
UM9830 - Microchip EOL Component | Discontinued Part
UM9830

UM9830 - Microchip EOL Component | Discontinued Part

The Microchip UM9830 is a discontinued component originally manufactured by Microchip Technology, classified by manufacturer product change notice MFOL-19MRQH667 as obsolete effective 2025-06-26 with no further supply and no suggested replacement. According to the referencesource.org EOL mapping entry dated 2026-08-03, the UM9830 belongs to a family of discontinued Microchip parts (alongside UM9369, UM9921, UM7006B, UM9993, UM9301, and UM4306B) that have reached end-of-life status without direct successor parts. Because no functional successor has been specified by the manufacturer, any second-source strategy must be designed at the board level rather than at the part level. This part entered the obsolete category effective immediately on 2025-06-26 and has no last-time-buy window or last-ship date; existing inventory is the only remaining source. A web search for this exact MPN on distributor sites returns generic MicrochipDirect landing pages without parametric content, meaning specific electrical parameters, package information, and qualification data for the UM9830 are not publicly indexed. Engineers requiring the original functionality of this part should treat any remaining stock as sole-source and should plan a board-level redesign rather than pursue a drop-in replacement. Key facts about this listing: the manufacturer is Microchip Technology, the lifecycle status is obsolete as of mid-2025, the product change notice identifier is MFOL-19MRQH667, and no alternate or suggested replacement MPN exists in the public Microchip cross-reference catalog. Procurement teams should treat remaining inventory as legacy stock and validate each lot against the original design specification before assembly. Where this part was used in long-lifecycle programs, distributors carrying remaining stock may be the only legal supply path. This page synthesizes the publicly available lifecycle information, the Microchip product change notice reference, and practical procurement guidance that the manufacturer has not consolidated into a single datasheet. Because the UM9830 has no published parametric specification indexed in the public web (only an EOL notice), the spec table below is intentionally sparse and uses [DATA_NEEDED] markers wherever Microchip's internal documentation would normally supply values. Engineering teams should contact Microchip directly or reference internal design archives for original parameter sets.

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UM9921 - Microchip Technology | XAIPART
UM9921

UM9921 - Microchip Technology | XAIPART

The Microchip Technology UM9921 is a component listed by Microchip Technology and distributed through authorized channels such as Arrow Electronics and indexed by Octopart, where it is categorized under the PIN (pin electronics / pin driver) product grouping. Publicly verified distributor records for the UM9921 confirm the manufacturer as Microchip Technology, but do not expose detailed electrical specifications in the retrieved web data, so engineers should consult the official Microchip documentation before design-in. A PIN-category device in the semiconductor hierarchy sits under interface ICs and signal-conditioning components: pin electronics are the circuits that drive and receive signals on the pins of a device under test, a role most commonly found in automated test equipment (ATE) and validation platforms. Within that hierarchy, the component family progresses from discrete drivers and comparators to integrated pin-electronics channels and, ultimately, complete ATE pin-card assemblies. Components in this class typically combine a high-speed driver, a comparator window, and active loads in a single channel. Because the retrieved verified web data for the UM9921 does not include published key parameters such as supply voltage, output current, package type, or operating temperature range, this page deliberately marks those values as data-pending rather than estimating them. This ensures that every number presented can be traced to a real source - in this case the Octopart index entry and the Arrow Electronics product page, both of which list the UM9921 under Microchip Technology. Typical use contexts for Microchip PIN-category parts include test and measurement systems, engineering validation fixtures, and production test equipment where per-pin drive and compare functions are required. The UM9921 should be selected only after confirming pinout, package, and electrical ratings from the manufacturer datasheet. Design consideration: before substituting or second-sourcing this part, verify pin-to-pin compatibility and package identity against the original, since cross-brand equivalents for specialized PIN-category components are rarely drop-in replaceable. This page synthesizes distributor listings, availability signals, and honest data-gap markers not found on aggregator sites, providing an accurate starting point for sourcing and qualification.

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UPD72874GC-YEB-A - IEEE 1394a OHCI 1.1 PHY-Link Host Controller | Renesas
UPD72874GC-YEB-A

UPD72874GC-YEB-A - IEEE 1394a OHCI 1.1 PHY-Link Host Controller | Renesas

The Renesas UPD72874GC-YEB-A is a single-chip IEEE 1394a OHCI 1.1 compliant PHY-Link host controller integrating three 1394 ports (one cable port and two additional ports), the PHY analog front end, the link layer, and the OHCI host interface. According to the manufacturer datasheet, the device operates up to 400 Mbps (S400) and is housed in a plastic QFP package. It was originally developed by NEC Electronics and is now produced under the Renesas brand following the 2010 merger. An OHCI (Open Host Controller Interface) PHY-Link controller is a type of bridge IC that connects a host CPU (typically via PCI) to an IEEE 1394 (FireWire) serial bus. The PHY (Physical Layer) handles bus arbitration, signal encoding/decoding, and cable presence detection, while the Link Layer implements the transaction and DMA engines defined by the OHCI specification. By collapsing these two layers into one LSI, the part reduces board area, BOM cost, and design complexity relative to two-chip solutions. Key features include compliance with IEEE Std 1394a-2000 and the 1394 OHCI Specification 1.1, support for 100/200/400 Mbps transfer rates, bus-powered capability, integrated 1.5 kV cable-port ESD protection (typical for the family), 3.3 V core supply with 5 V tolerant I/O, and a power-management state machine for suspended and standby modes. The host bus interface conforms to PCI 2.1 with a 32-bit data path at up to 33 MHz. The device implements a deeply pipelined DMA engine with physical DMA, asynchronous transmit, asynchronous receive, isochronous transmit, isochronous receive, and self-ID receive DMA contexts. Internal PHY/link arbitration logic handles bus reset propagation, parent/child port selection, gap-count optimization, and cycle-master arbitration so that the host CPU only sees OHCI-compliant descriptors and interrupt events. Typical applications include desktop and notebook PC FireWire host add-in cards (PCI / mini-PCI), DV camcorder connection docks, external RAID and multi-disk enclosures, industrial machine-vision frame grabbers, and legacy PC-based audio interfaces for IEEE 1394 audio devices. Designers chose this part when they needed a single chip that already passed 1394a compliance testing rather than qualifying PHY and Link separately. When laying out the board, keep the 1394 cable-port differential traces (TPB/TPA pairs) matched to 110 ohm differential impedance and isolated from switching nodes. Decouple each VCC pin with a 0.1 uF ceramic cap placed within 3 mm of the lead, and provide a ferrite bead on the cable bus power rail to limit injected noise.

USD $9,75 En stock
UPD78F0532AGB-GAH-AX - 8-Bit 20MHz 24KB Flash MCU | Renesas
UPD78F0532AGB-GAH-AX

UPD78F0532AGB-GAH-AX - 8-Bit 20MHz 24KB Flash MCU | Renesas

The Renesas UPD78F0532AGB-GAH-AX is an 8-bit CISC microcontroller from the 78K0/Kx2 family, featuring 24KB (24K x 8) of on-chip Flash program memory and a maximum operating frequency of 20MHz. Housed in a 64-pin LQFP package, the device operates from a 1.8V to 5.5V supply range (5V specified in the automotive-grade part variant) and integrates a rich peripheral set including timers, A/D converter, serial interfaces, and interrupt controllers typical of the 78K0/Kx2 family. An 8-bit microcontroller (MCU) is a single-chip computer built around an 8-bit data path, optimized for cost-sensitive, low-power embedded control. Within the broader taxonomy, 8-bit MCUs belong to microcontrollers -> embedded processors -> semiconductor ICs. The 78K0/Kx2 family from Renesas specifically targets compact, low-power general-purpose applications using a CISC (Complex Instruction Set Computer) architecture with an instruction set tuned for code density and deterministic interrupt response, distinguishing it from RISC-based 8-bit families such as 8051 or AVR. Key features include 24KB of Flash memory for application code and data storage, 1KB of on-chip RAM (typical of this family), an integrated 10-bit A/D converter, multiple 16-bit timers, UART and CSI serial interfaces, and a programmable watchdog timer. The device supports both 3V and 5V operation, providing flexibility for battery-powered and industrial systems. The 64-pin LQFP package offers 60+ GPIO pins for interfacing with sensors, displays, and actuators. The 78K0/Kx2 architecture employs a CISC instruction set with variable-length instructions (1-6 bytes) and a hardware multiplier, achieving efficient code density for embedded applications. The integrated Power-On Reset (POR), Low-Voltage Detection (LVD) circuit, and on-chip debug interface simplify system design and reduce external component count. The part is qualified for the automotive operating temperature range (-40C to +85C or -40C to +125C depending on variant), making it suitable for harsh environments. Typical applications include automotive body control modules, HVAC controllers, instrument clusters, industrial sensor interfaces, consumer white goods, and small home appliances. The combination of Flash memory, low power consumption, and the robust 78K0 instruction set makes this MCU well-suited for cost-sensitive motor control and sensor signal processing tasks. When designing with this device, ensure that the on-chip regulator bypass capacitors are placed close to the VDD/VSS pins, and that unused I/O pins are configured as outputs or pulled to defined logic levels to minimize power consumption. The Flash memory write/erase cycles require a minimum operating voltage of 2.7V; for battery-backed designs, plan for brown-out detection. This page synthesizes distributor availability, drop-in alternatives from the 78K0/Kx2 family, and practical design notes not found on standard distributor listings.

USD $5,10 En stock
USB20H04-JT - 4-Port USB 2.0 Hub Controller | SMSC
USB20H04-JT

USB20H04-JT - 4-Port USB 2.0 Hub Controller | SMSC

The SMSC USB20H04-JT is a four-port USB 2.0 hub controller with four downstream ports, four transaction translators, I2C, SMBus, and serial host interfaces, supplied in a 64-pin TQFP package measuring 10 mm by 10 mm. It supports operating-temperature conditions from 0°C to 70°C and accepts the verified 1.74 V to 2 V and 3 V to 3.6 V supply ranges. A USB hub controller is an interface semiconductor that manages traffic between one upstream USB host and multiple downstream devices. It belongs to the USB interface-controller hierarchy and coordinates attachment, enumeration, power management, and data transfer so that peripheral devices can share one host controller. The USB20H04-JT targets USB 2.0 hubs requiring multiple high-speed downstream ports. Four transaction translators are the device's principal architectural feature and help maximize USB throughput when devices on different downstream branches transfer data concurrently. The controller supports OTG-compatible USB devices and bus-powered Hi-Speed hub designs, making it useful in compact external hubs, docking stations, printers, storage systems, and embedded USB equipment. Its stated supply current is 135 mA, which must be included in hub power-budget calculations. The USB20H04-JT supports serial, I2C, and SMBus host-side connectivity, allowing firmware or an external controller to supervise hub behavior. Its lead-free construction and surface-mount format support automated PCB assembly, although the 64-pin TQFP package requires careful fanout and exposed-pad-free thermal review. The component is identified as CMOS and TQFP-64 in distributor records. For design work, route USB differential pairs as controlled-impedance, length-matched connections and keep supply decoupling close to the device. The verified material does not provide a complete pinout, electrical limits table, supported current budget, or detailed timing values in the supplied text, so those details must be verified in the manufacturer datasheet before schematic release or USB compliance testing. This product data consolidates verified distributor specifications, the identified USB2504 migration path, sourcing references, and practical design cautions. Engineers should treat the USB2504 family as a documented migration option, not as an automatically interchangeable replacement until package pinout, firmware, clock, power, and USB compliance requirements are checked.

USD $2,65 En stock
USB2412-DZK - 2-Port USB 2.0 Hub Controller | Microchip
USB2412-DZK

USB2412-DZK - 2-Port USB 2.0 Hub Controller | Microchip

The Microchip USB2412-DZK is a low-power, two-port USB 2.0 hub controller IC using a single Transaction Translator architecture, with a 3 V to 3.6 V supply range and support for low-speed, full-speed, and high-speed downstream devices in a 28-QFN package. It is designed for embedded USB hub applications requiring two downstream ports and USB 2.0 Hi-Speed operation. A USB hub controller is an interface IC that manages traffic between one upstream USB host connection and multiple downstream USB ports. The USB2412 belongs to the USB interface-controller hierarchy, where USB 2.0 connectivity, transaction translation, port management, and embedded system integration combine into a dedicated hub solution. Its single Transaction Translator, or STT, architecture is intended to reduce implementation complexity in compact USB hub designs. The verified product information identifies two downstream ports, USB 2.0 operation, low-power operation, and support for low-speed, full-speed, and high-speed downstream devices when the hub operates at high speed. The controller is available in a 28-QFN package, while distributor records identify the package as 28-VFQFN with an exposed pad. The USB interface supports system integration with embedded USB host, peripheral, docking, and industrial equipment designs. The 3 V to 3.6 V operating supply range places the device in a low-voltage digital interface class. USB data integrity depends on correct PCB routing, adequate power distribution, compliant connector implementation, and proper decoupling. The exposed-pad package requires attention to thermal and layout practices, even though the verified snippets do not provide a complete electrical limit table or detailed power-consumption values. Typical applications include two-port embedded USB hubs, self-powered USB equipment, industrial control systems, test and measurement fixtures, docking equipment, and compact host systems that need USB device expansion. The two-port architecture is useful when a system must connect peripherals without adding multiple independent host controllers. When selecting a replacement, verify the complete pinout, package dimensions, exposed-pad connection, USB signal routing, clock requirements, and power sequencing against the original design. The USB2412-DZK-TR is a tape-and-reel ordering variant, while other listed controllers or transceivers may provide different functions and must not be treated as drop-in substitutes without manufacturer verification. This page consolidates the verified manufacturer description, distributor package data, official datasheet link, application guidance, and cross-reference findings to support engineering selection. It distinguishes confirmed USB2412 attributes from parameters that require the manufacturer datasheet or an authorized design review.

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USB2422-CP - Low-Power 2-Port USB 2.0 Hub Controller | Microchip Technology
USB2422-CP

USB2422-CP - Low-Power 2-Port USB 2.0 Hub Controller | Microchip Technology

The Microchip Technology USB2422-CP is a low-power, single-transaction-translator USB 2.0 hub controller with two downstream ports, packaged in a 24-QFN (4x4 mm) package. It supports an upstream Hi-Speed and Full-Speed hub connection or a Full-Speed-only configuration, while downstream devices can operate at Low-Speed, Full-Speed, or Hi-Speed when configured as a Hi-Speed hub. The controller is designed for embedded USB expansion systems requiring compact bus routing and USB 2.0 compatibility. Its two-port architecture integrates downstream-port USB connectivity into one controller rather than requiring separate hub devices. A USB hub controller is an interface IC within the broader USB interface-controller and semiconductor hierarchy. In an embedded system, the upstream port connects the hub to a host controller, while each downstream port connects external peripherals such as storage, keyboards, communications modules, or service interfaces. USB2422-CP acts as the transaction translator and hub-management element between those connections, helping the host system organize USB traffic across two ports. Its support for Full-Speed and Hi-Speed operation makes it relevant to legacy USB 2.0 embedded designs rather than modern USB 3.x or USB4 systems. The principal verified feature set includes a 2-port USB 2.0 hub configuration, single transaction translator operation, upstream Hi-Speed and Full-Speed attachment capability, and downstream Low-Speed, Full-Speed, and Hi-Speed support. Microchip describes the device as low power, which is valuable in embedded equipment where USB expansion must not dominate the system power budget. The 24-QFN package provides a compact surface-mount footprint, but its exposed thermal and electrical requirements must be handled according to the manufacturer datasheet. The controller is positioned between a USB host and downstream USB peripherals. When configured as a Hi-Speed hub, the upstream link and compatible downstream links can use USB 2.0 Hi-Speed operation; when used as a Full-Speed-only hub, the design avoids requiring Hi-Speed operation. Device attachment, removal, enumeration, and power-management behavior must be evaluated against the USB host software and the electrical requirements of the connected peripherals. The verified web data does not provide current unit pricing, stock status, lead time, detailed pin names, or all electrical timing and current limits, so those values are not inferred here. Typical applications include embedded instrumentation, industrial control panels, compact USB expansion boards, peripheral consolidation, and USB connectivity in systems that already use a USB 2.0 host controller. A hub may be useful when a processor exposes one host port but the enclosure requires two external connections. The design should verify connector protection, power switching, cable length, chassis grounding, and host compatibility. The manufacturer datasheet is the authoritative source for pin assignments, electrical limits, configuration registers, and implementation details. Use the USB2422-CP when the existing PCB is designed around its 24-QFN footprint and the application needs a compact two-port USB 2.0 hub controller. Confirm package pin compatibility, operating conditions, and USB host requirements before treating any substitute as a drop-in replacement. This page combines verified manufacturer descriptions, distributor package information, datasheet references, application context, and procurement guidance. It distinguishes documented facts from missing parameters and avoids inventing prices, pin assignments, electrical limits, or replacement parts.

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USB2422-I/MJ - 2-Port USB 2.0 Hub Controller | Microchip
USB2422-I/MJ

USB2422-I/MJ - 2-Port USB 2.0 Hub Controller | Microchip

The Microchip Technology USB2422-I/MJ is a low-power, single-transaction-translator USB 2.0 hub controller with two downstream ports, 3.3 V operation, and a 24-QFN 4x4 mm package. It supports Low-Speed, Full-Speed, and Hi-Speed downstream devices when configured as a Hi-Speed hub, while the upstream connection can operate as a Hi-Speed and Full-Speed hub or as a Full-Speed-only hub. A USB hub controller is an interface IC that manages one upstream USB connection and multiple downstream USB ports. Within the broader hierarchy of USB interface controllers, the USB2422 combines port routing, power-switch control, overcurrent protection, internal voltage regulation, and USB signal conditioning in one compact device for embedded systems. The part includes BC1.1 protocol support, downstream port power-switch control, overcurrent protection, an internal regulator, and ESD protection. Required USB port resistors are integrated, including D+ and D- series-termination resistors and the specified pull-down or pull-up resistors. Internal pull-ups are also provided for downstream overcurrent-sense inputs, reducing external component count. Its single-translation-translator architecture serves embedded USB applications in which low power, compactness, and upstream-device integration matter more than independent simultaneous translation on every downstream port. The device can therefore support compact host ports in equipment that otherwise lacks native USB hub routing. Typical uses include industrial control panels, medical equipment, printers, embedded test systems, set-top boxes, and other USB 2.0 equipment requiring two downstream connections. Applications should account for the hub's single-translator architecture and verify downstream-device compatibility before final system release. PCB implementation should preserve the manufacturer's recommended USB trace geometry, place decoupling and support components near their associated pins, and route differential D+ and D- paths as a matched pair. USB signal integrity depends on controlled impedance, minimized stubs, and uninterrupted return-path continuity across the connector, controller, and protection circuitry.

USD $1,16 En stock
USB2422/MJ - 2-Port USB 2.0 Hub Controller | Microchip
USB2422/MJ

USB2422/MJ - 2-Port USB 2.0 Hub Controller | Microchip

The Microchip Technology USB2422/MJ is a low-power, single-transaction-translator, two-port USB 2.0 hub controller for embedded USB solutions. It supports one upstream port and two downstream ports in a 24-QFN package measuring 4 mm by 4 mm. The controller can operate as a Hi-Speed and Full-Speed hub or as a Full-Speed-only hub, while downstream devices may use Low-Speed, Full-Speed, or Hi-Speed when the hub is configured for Hi-Speed operation. A USB hub controller is an interface integrated circuit that manages traffic between one upstream USB host connection and multiple downstream ports. Within the USB interface hierarchy, it belongs to the class of USB controllers and hub-controller devices used to expand USB connectivity in embedded systems. Unlike a host-controller interface that directly manages a host bus, the USB2422/MJ translates USB traffic for attached downstream devices and centralizes hub functions. The verified product information identifies the USB2422 as a two-port USB 2.0 Hi-Speed hub controller. Microchip states that all required USB-port resistors are integrated, including the series termination resistors and the required pull-down and pull-up resistors on D+ and D- pins. The downstream-port over-current sense inputs also have internal pull-up resistors. These integrated functions can reduce external discrete-component count while simplifying PCB layout. The single-translation architecture is a key engineering distinction. It uses one transaction translator for the two downstream ports rather than assigning an independent translator to every port. This can be suitable for embedded USB expansion where the application does not require maximum simultaneous transaction concurrency. By contrast, Microchip identifies USB2512B as a Multiple Transaction Translator design for applications needing more performance or parallel downstream-port operation. Typical uses include embedded instrumentation, industrial control equipment, printers, test systems, set-top equipment, and other USB-enabled products that need two downstream connections from one embedded host interface. The exact upstream and downstream interface rates, electrical limits, pin names, clock requirements, and operating-temperature details must be confirmed in the manufacturer datasheet before layout or firmware development. For robust implementation, follow the USB2422 Hardware Design Checklist and preserve the required USB routing, termination, bypass, and grounding practices. The 24-QFN footprint also demands careful thermal-pad assembly and adequate exposed-pad copper. Because the supplied distributor snippets do not provide a complete pinout, this record avoids inventing pin assignments and marks missing technical values explicitly where required. This page consolidates the verified Microchip product description, distributor listings, datasheet links, and hardware-design references. It also distinguishes a true package-compatible replacement from merely similar USB hub controllers, which is essential because USB hubs may differ in translator architecture, pinout, package, clocking, and host-interface requirements.

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USB2422T/MJ - 2-Port USB 2.0 Hub Controller | Microchip
USB2422T/MJ

USB2422T/MJ - 2-Port USB 2.0 Hub Controller | Microchip

The Microchip Technology USB2422T/MJ is a low-power, two-port USB 2.0 hub controller with a single transaction translator, designed for embedded USB hub implementations. It supports High-Speed and Full-Speed operation on the upstream side, while downstream devices can operate at Low-Speed, Full-Speed, or High-Speed when the hub is configured for High-Speed operation. The device is supplied in a 24-QFN 4 x 4 mm package. A USB hub controller is an interface IC that manages traffic between an upstream host and multiple downstream USB peripherals. The USB2422 combines the physical-layer connectivity, port management, transaction translation, and hub-specific control functions required to expand one host USB port into two downstream ports. It belongs to the USB interface controller hierarchy, which sits within interface ICs and broader embedded semiconductor systems. The controller integrates the required USB port resistors, including series termination resistors on D+ and D-, pull-down and pull-up resistors on D+ and D-, and internal pull-ups for the downstream over-current sense inputs. This integration reduces external discrete-component count and simplifies embedded hub-board layouts. The upstream interface can operate as a High-Speed and Full-Speed hub or as a Full-Speed-only hub, providing configuration flexibility for different host links and legacy peripherals. Microchip specifies conformance with the SMBus 1.0 voltage, power, and timing characteristics for slave-only devices except where Section 4.3 specifies otherwise. This makes the controller relevant to managed USB connectivity designs that use SMBus sideband signaling. Its two downstream ports are intended for embedded docking stations, compact equipment, industrial panels, and other USB expansion systems where external discrete hub electronics would add complexity. Typical applications include USB-to-USB port expansion, embedded test and measurement equipment, industrial control panels, media appliances, and compact host systems. The 4 x 4 mm QFN package supports space-constrained designs, but exposed-pad layout and thermal management must follow the manufacturer's recommended land pattern. When designing with the USB2422T/MJ, preserve the D+ and D- geometry, provide the required USB connection and bypass components, and use the package's exposed thermal pad as a low-impedance ground and heat-spreading path. Verify upstream and downstream operating-mode configuration, suspend behavior, and over-current handling in the complete system rather than assuming standard desktop-hub behavior. This page consolidates the verified manufacturer and distributor information, explains the USB2422's integration benefits, identifies practical design constraints, and separates confirmed drop-in alternatives from candidates that require footprint verification before substitution.

USD $1,04 En stock
USB2502-AEY - 2-Port USB 2.0 Hub Controller | SMSC
USB2502-AEY

USB2502-AEY - 2-Port USB 2.0 Hub Controller | SMSC

The SMSC USB2502-AEY is a 2-port USB 2.0 hub controller that connects one upstream host port to two downstream-facing USB ports. The verified product material identifies support for Low-Speed operation at 1.5 Mb/s and Full-Speed operation at 12 Mb/s; when attached to a High-Speed host, both downstream ports can also support High-Speed operation at 480 Mb/s. It is available in a QFN package. A USB hub controller is an interface semiconductor within the broader USB interface-controller hierarchy. Its function is to manage traffic from one USB host connection across multiple downstream ports while supporting the speed modes permitted by USB 2.0. Configuration can be handled through strapping options, an external EEPROM, or a microcontroller interface; with a microcontroller, the hub operates as an SMBus slave device. The principal engineering benefits are its two-port integration, upstream Full-Speed or High-Speed attachment, and configurable setup. Downstream devices may operate at Low-Speed, Full-Speed, or High-Speed when the hub is attached to a High-Speed host. This allows one controller to serve keyboards, storage, communications adapters, and other USB peripherals without requiring separate upstream controllers. Technical implementation requires careful treatment of USB signal integrity, power distribution, grounding, and enumeration. The controller coordinates device attachment and port behavior, but the final system must still meet USB 2.0 layout, capacitance, and power requirements. Exact electrical limits, pin assignments, clock requirements, and package dimensions must be taken from the Microchip manufacturer datasheet rather than inferred from marketplace listings. Typical uses include compact USB hubs, embedded host systems, docking equipment, peripheral expanders, and industrial adapters. In these systems, USB2502-AEY provides the multi-port coordination logic while external power switches, connectors, crystal or clock circuitry, and supporting passives implement the physical USB interface. Exact bill-of-material requirements should be confirmed against the datasheet reference implementation. For USB hub layouts, keep high-speed traces short and controlled, provide continuous return paths, place required decoupling close to the device, and validate differential impedance and connector placement in the assembled board. The available data does not state the package pin count, operating-temperature range, voltage limits, or full ordering-code characteristics, so those values must not be guessed.

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USB2502-HD - 2-Port USB 2.0 Hub Controller | Microchip
USB2502-HD

USB2502-HD - 2-Port USB 2.0 Hub Controller | Microchip

The Microchip USB2502-HD is a two-port USB 2.0 hub controller that complies with the Universal Serial Bus Specification Revision 2.0 and operates as a full-speed hub or a full-/high-speed hub. Its two enabled downstream ports support low-speed devices at 1.5 Mb/s, full-speed devices at 12 Mb/s, and high-speed devices at 480 Mb/s when operated with a high-speed host. It is packaged as an integrated circuit, but the verified sources do not specify the exact package variant or dimensions. A USB hub controller is an interface semiconductor that expands one host USB connection into multiple downstream ports. It belongs to the USB interface controller hierarchy, alongside transceivers, host controllers, and device controllers. The hub manages enumeration, port power, connect and disconnect events, and transaction routing while allowing multiple USB peripherals to share one upstream host port. The principal feature of USB2502-HD is support for two downstream-facing ports and USB 2.0 operation. Low-speed, full-speed, and high-speed device support provides compatibility with keyboards, mice, storage devices, printers, and other USB peripherals. The controller can attach to a full-speed host or a higher-speed host, with downstream high-speed operation available when the hub is connected in the required high-speed configuration. Technically, USB2502-HD integrates the hub-control function into a dedicated interface IC rather than requiring a general-purpose processor. According to the Microchip USB2502 datasheet, the device is fully compliant with the Universal Serial Bus Specification Revision 2.0 dated April 27, 2000, including the cited errata. The available verified data does not state operating voltage, clock frequency, transceiver current, temperature range, pin count, or package dimensions. Typical uses include USB expansion in embedded systems, industrial control equipment, test instruments, printers, storage enclosures, and computer peripherals. The two-port architecture is useful when one host port must connect to two accessories while retaining support for both legacy and high-speed USB devices. Existing board revisions should be checked against the manufacturer package drawings before layout reuse or substitution. The most important design consideration is that a hub is only one part of the USB channel design. Upstream and downstream routing, connector placement, power-supply capacity, decoupling, ground continuity, and USB signal-integrity layout can determine whether advertised 480 Mb/s operation is reliable. Use the complete Microchip datasheet and its reference circuit for component values, layout geometry, and validation requirements. This product page consolidates the verified USB2502-HD commercial information, USB speed capabilities, official datasheet link, and sourcing details. It does not invent unavailable electrical or package specifications, and it distinguishes verified USB behavior from values that still require datasheet confirmation.

USD $1,57 En stock