Circuitos integrados

10CX085YU484I5G

10CX085YU484I5G - Cyclone 10 GX FPGA 85K LE | Intel | FPGA

The Intel 10CX085YU484I5G is a Cyclone® 10 GX field-programmable gate array (FPGA) built on a 20 nm process, integrating 85,000 logic elements, 5,959,680 bits of embedded memory, and 188 user I/O pins in a 484-pin UBGA (Ultra-fine-pitch Ball Grid Array) package. It supports transceiver data rates up to 12.5 Gbps and is targeted at high-volume, cost-sensitive applications that still require hardened transceivers, DSP blocks, and PCI Express Gen2 hard IP. A Cyclone 10 GX FPGA belongs to Intel's mid-range FPGA family — specifically the low-power, transceiver-equipped tier optimized for industrial, video, and connectivity use cases. Within the broader product hierarchy, it sits below the Arria 10 and Stratix 10 families: Cyclone 10 → low-power FPGA family → FPGA → programmable logic device → semiconductor IC. Its design tool is the Quartus Prime Lite/Standard/Pro software suite. Key features include 85K logic elements, 156 (18x18) multipliers, embedded memory of 5,959,680 bits, four 12.5 Gbps transceivers, two PCI Express Gen2 hard IP blocks, and hard memory controllers. Industrial temperature grade (-40 °C to +100 °C) makes it suitable for harsh environments. The 484-pin UBGA package combines high pin count with a compact 19 mm × 19 mm footprint suitable for mid-complexity designs. Architecturally, the device uses a 20 nm TSMC process with a fabric composed of Adaptive Logic Modules (ALMs), M20K embedded memory blocks, variable-precision DSP blocks, and a hardened periphery containing transceivers, PLLs, and PCIe Gen2 controllers. Hardening these functions reduces logic consumption and improves timing closure compared to soft implementations. Typical applications include industrial machine vision, broadcast video processing, motor control, smart-grid terminals, and PCI Express endpoint cards in embedded systems. The combination of low power, transceivers, and PCIe Gen2 hard IP enables single-chip solutions where previous designs required a discrete ASSP plus an FPGA. When designing with the 10CX085YU484I5G, pay attention to transceiver channel placement (only available on specific banks), power-supply sequencing of the core and transceiver rails, and the requirement for a JTAG configuration interface during development. Quartus Prime must be selected for the GX family. This page synthesizes distributor pricing, same-package pin-compatible OPN alternatives within the Cyclone 10 GX family, and practical design notes not consolidated in the manufacturer datasheet.

USD $85,00 En stock

10CX085YU484I6G

10CX085YU484I6G - 85K LE Cyclone 10 GX FPGA, 484-FBGA | Intel / Altera

The Intel / Altera (formerly Altera) 10CX085YU484I6G is a Cyclone® 10 GX field-programmable gate array (FPGA) with 85,000 logic elements, 5,959,680 bits of embedded memory, 31,000 adaptive logic modules (ALMs), and 188 user I/Os, housed in a 484-pin FineLine BGA (UBGA) package. It operates from a 0.9 V core supply with industry-standard 1.0 V/1.2 V/1.5 V/1.8 V/2.5 V/3.3 V multi-voltage I/O support and is rated for the industrial temperature range of -40 °C to +100 °C. A field-programmable gate array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and programmable interconnect that can be re-programmed in-system to implement arbitrary digital logic, signal-processing pipelines, or interface protocols. Within the broader taxonomy, an FPGA is a type of programmable logic device (PLD) -> programmable logic -> semiconductor IC. The Cyclone 10 GX family specifically targets cost-sensitive high-volume applications that need transceivers, making it a member of Intel's low-end FPGA portfolio. Key features of the 10CX085YU484I6G include 12.5 Gbps GX transceivers for high-speed serial links, hardware floating-point DSP blocks for digital signal processing acceleration, and embedded hard memory controllers. The device supports up to 6.473 Mbits of embedded memory distributed across M20K block memory and MLAB resources, enabling high-throughput data buffering without external SRAM. Configuration is supported through JTAG, AS, PS, and FPP modes with optional encryption using AES-256 bitstream security. The 10CX085YU484I6G uses a TSMC 20 nm process and an adaptive logic module (ALM) architecture that delivers 1.5x the logic capacity of the previous Cyclone generation per ALM. This makes it well suited for parallel processing, high-speed bridging, and protocol conversion where multiple interface standards coexist on a single board. Typical applications include industrial machine vision, video surveillance with on-device analytics, motor control and industrial automation, military and aerospace avionics subsystems, broadband access equipment, and PCI Express Gen2 endpoint designs. The integrated transceivers also enable 10 GbE and CPRI links for wireless fronthaul. When designing with this device, allocate adequate power decoupling (100 nF + 10 µF per supply rail) and follow Intel's power-rail sequencing guidelines. Use the Quartus Prime design suite (Lite / Standard / Pro editions depending on device utilization) for synthesis, place-and-route, and timing closure. This page synthesizes verified distributor pricing, drop-in same-family alternatives, application guidance, and design considerations not found on the manufacturer datasheet alone.

USD $155,60 En stock

10CX105YF672E5G

10CX105YF672E5G - Cyclone 10 GX FPGA 104K LE | Intel | 672-FCBGA

The Intel 10CX105YF672E5G is a Cyclone 10 GX field-programmable gate array (FPGA) integrating 104,000 logic elements, 7,640 Kbit of embedded SRAM, and 236 user I/Os in a 672-ball FCBGA package. Built on a 20 nm process, it provides 152,000 registers, 250 18x19 multipliers, 6 PLLs/DLLs, and 382 total block RAM blocks, plus 3.125 Gbps transceivers typical of mid-range Cyclone 10 GX devices. An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic fabric, memory blocks, and I/O cells can be reconfigured after manufacture, sitting in the hierarchy: logic cell -> logic array block (LAB) -> FPGA -> programmable logic device (PLD) -> integrated circuit. The Cyclone 10 GX family targets cost- and power-sensitive applications that still need transceivers and DSP blocks for video, industrial, and wireless bridging. Key features include 0.9 V core operation, six PLLs/DLLs for clock management, dedicated 18x19 multipliers for DSP, embedded SRAM blocks totaling 7,640 Kbit, and JTAG-based configuration via SRAM. The device family is known for low static and dynamic power relative to other 20 nm FPGAs and offers hardened memory controllers and PCIe Gen2 hard IP. Technical depth comes from the 20 nm TSMC process, an adaptive logic module (ALM) architecture, and hardened transceiver blocks that offload high-speed serial I/O from soft logic. With 382 block RAM instances, designers can implement wide FIFOs, packet buffers, and on-chip frame storage without burning logic resources. Typical applications include industrial machine vision, video bridging and protocol conversion, low-cost wireless backhaul, motor and motion control, and IoT edge aggregation. Its combination of transceivers and DSP suits parallel processing pipelines. When designing with this FPGA, plan power sequencing for the 0.9 V core and 1.8/2.5/3.3 V I/O banks separately, and use the Intel Quartus Prime toolchain for synthesis, place-and-route, and timing closure on Cyclone 10 GX. This page synthesizes distributor pricing, drop-in alternative MPNs from the Cyclone 10 GX family, and practical PCB thermal and signal-integrity guidance not consolidated in the manufacturer datasheet.

USD $310,00 En stock

10CX105YF672E6G

10CX105YF672E6G - Cyclone 10 GX FPGA, 105K LE, 672-FBGA | Intel / Altera

The Intel / Altera (formerly Altera) 10CX105YF672E6G is a Cyclone® 10 GX field-programmable gate array (FPGA) integrating 105,000 logic elements (104,000 cells) and 8,641,536 bits of embedded memory (8.439 Mbit) into a 672-ball FineLine BGA (FBGA/FCBGA) package with 236 user I/Os. It belongs to the low-power, transceiver-rich Cyclone 10 GX family, targeting cost- and power-sensitive applications with up to 12.5 Gbps transceiver support. An FPGA (Field-Programmable Gate Array) is a programmable logic device (PLD) category of integrated circuits that combines programmable logic blocks, interconnect, memory, and increasingly hardened IP (transceivers, DSP blocks, processors) on a single die. FPGAs sit in the broader hierarchy of programmable logic devices -> programmable logic -> digital semiconductor -> integrated circuit. Compared with ASICs, FPGAs offer rapid prototyping, in-system reconfiguration, and lower NRE costs at the expense of unit price, power, and absolute performance. Key features of the 10CX105YF672E6G include 38,000 adaptive logic modules (ALMs), 0.9 V core operating voltage, 6.875 Gb/s (CX suffix denotes the speed grade) per-transceiver data rate, hardened PCI Express Gen2 and external memory controllers, and a commercial 0°C to +100°C operating range. The 672-FBGA package supports high-density board designs while remaining SMD/SMT compatible with standard reflow profiles. The device uses a TSMC 20 nm process and a logic-structure architecture with embedded SRAM blocks, MLABs, DSP blocks, and 12 transceiver channels capable of handling common serial protocols (PCIe, Gigabit Ethernet, CPRI, JESD204B). The -E6 speed grade balances timing margin and power, making it suitable for general-purpose industrial and video/imaging pipelines. Typical applications include industrial video bridging and machine-vision interfaces, low-cost PCIe Gen2 endpoint cards, IoT edge acceleration, motor and motion control, broadcast and pro-AV signal processing, and factory automation backplanes. The Cyclone 10 GX family is widely chosen where Cyclone V or Cyclone IV designs need an upgrade path with more transceivers, more logic, and lower static power. When designing with this FPGA, plan power sequencing for the 0.9 V core rail and the transceiver/auxiliary rails separately, and place decoupling within the package's recommended via pattern. Quartus Prime design software is required for synthesis, place-and-route, and bitstream generation, and the 10CX105YF672E6G is supported by the Quartus Prime Standard edition. This page synthesizes distributor pricing, drop-in Cyclone 10 GX package-pin-compatible alternatives, and practical design notes not found on the manufacturer product page alone, including speed-grade migration guidance and pin-compatible density options.

USD $100,55 En stock

10CX105YF672I5G

10CX105YF672I5G - Cyclone 10 GX FPGA, 104K LE, F672 | Intel

The Intel (formerly Altera) 10CX105YF672I5G is a Cyclone 10 GX field-programmable gate array (FPGA) featuring 104,000 logic elements, 8,641,536 bits of embedded memory, and 236 user I/O pins, housed in a 672-ball flip-chip BGA (F672 / BBGA) package. It is the industrial temperature grade variant of the 10CX105 device family, optimized for low-cost, high-volume applications requiring integrated transceivers and hardened memory controllers. An FPGA (field-programmable gate array) is a semiconductor device built around an array of configurable logic blocks (CLBs) connected via programmable routing, allowing designers to implement custom digital logic, signal processing pipelines, and interface protocols after fabrication. Cyclone 10 GX sits within Intel's low-power, cost-optimized FPGA hierarchy, positioned below the high-performance Stratix 10 family and above the Cyclone V / Cyclone IV families. Within the Cyclone 10 GX family, the 10CX105 is the largest member, integrating up to 12.5 Gbps transceivers and hardware hardened PCI Express Gen2 and external memory interfaces, making it a true System-on-Chip (SoC FPGA) for cost-sensitive applications. Key features include 156 18x19 multipliers for digital signal processing, support for DDR3/DDR4/LPDDR3 external memory interfaces with dedicated hard memory controllers, and 12 integrated transceivers capable of data rates up to 12.5 Gbps. The device also includes a hard PCIe Gen2 IP block with x1/x2/x4 lane support. The F672 package uses Intel's flip-chip BGA technology to maximize signal integrity and I/O density, with a fine 1.0 mm ball pitch that enables compact PCB designs. Architecturally, the 10CX105 implements an adaptive logic module (ALM) fabric with 8-input fracturable look-up tables (LUTs), providing approximately 25% higher logic utilization than previous-generation Cyclone devices. The transceiver blocks use hardened PCS/PMA logic, enabling serial protocols such as PCIe, GbE, SGMII, JESD204B, CPRI, and SMPTE SDI without consuming soft logic fabric. Built-in hard IP blocks (PCIe Gen2 x4, memory controllers, PLLs) reduce soft logic usage and improve timing closure on cost-sensitive designs. Typical applications include industrial machine vision and video processing pipelines, factory automation and motor control, low-cost wireless backhaul equipment, broadcast video (12G-SDI) interfaces, and PCIe acceleration cards for industrial PCs. Designers should pay attention to transceiver reference clock jitter (sub-500 fs RMS recommended for 10+ Gbps links), PCB-controlled impedance for high-speed serial routing (85 ohm differential), and thermal management for applications with sustained high transceiver utilization.

USD $108,00 En stock

10CX105YF672I6G

10CX105YF672I6G - Cyclone 10 GX FPGA, 105K LE, 672-BGA | Intel

The Intel (formerly Altera) 10CX105YF672I6G is a Cyclone® 10 GX field-programmable gate array (FPGA) with 104,000 logic elements, 236 user I/Os, and 8,641,536 bits of embedded memory, housed in a 672-ball fine-pitch BGA (FCBGA) package. Built on TSMC's 20 nm process, the device integrates 3,800 adaptive logic modules (ALMs), up to 7.46 Mbit of embedded SRAM, and dedicated hardware for high-throughput transceivers and DSP blocks. The 'I6G' suffix indicates the industrial temperature grade (-40°C to +85°C), lead-free / RoHS-compliant assembly, and a -6 speed grade aimed at mid-tier transceiver and logic performance. A Field Programmable Gate Array (FPGA) is a class of programmable logic device that allows designers to configure arbitrary digital logic, memory blocks, and I/O protocols after PCB fabrication. Cyclone 10 GX FPGAs are positioned in Intel's mid-range portfolio for cost-sensitive applications requiring integrated transceivers (up to 12.5 Gbps), hard PCIe Gen2 controllers, and a rich DSP block fabric. They occupy a tier between low-power Cyclone 10 LP parts and high-end Stratix 10 devices, balancing logic density against power and unit cost. Key features of the 10CX105YF672I6G include a 105K LE fabric optimized for parallel processing pipelines, hard memory controllers for DDR3/DDR4/LPDDR3 external memory interfaces, up to 3.75 Gbps LVDS-capable GPIO, and embedded PCI Express Gen2 x4 hard IP. The 672-pin FCBGA package exposes 236 general-purpose I/Os and 12 transceiver channels for high-speed serial connectivity. Configuration is supported via JTAG, AS, PS, and FPP modes through dedicated configuration pins. Typical applications include industrial machine vision, video broadcasting, factory automation controllers, low-cost 10G Ethernet aggregation, software-defined radio front-ends, and PCIe-based accelerator cards. The combination of transceiver channels, hard PCIe cores, and DSP blocks makes it a versatile fabric for protocol bridging and parallel compute offload. The industrial temperature grade supports deployment in factory floor and outdoor enclosures without additional thermal derating. When designing with the 10CX105YF672I6G, ensure PCB design follows Intel's FCBGA land pattern and high-speed transceiver routing guidelines. Power supply sequencing requires careful ramp coordination between core and I/O rails to avoid in-rush current damage. Use Intel Quartus Prime software for synthesis, place-and-route, and bitstream generation. Thermal management relies primarily on PCB copper and forced airflow; the package does not integrate a discrete heatsink. This page synthesizes distributor pricing, drop-in Cyclone 10 GX alternatives, and PCB layout considerations not consolidated on the manufacturer product page. All specifications are sourced from the verified Intel/Altera Cyclone 10 GX device datasheet and current distributor listings as of 2026-09-05.

USD $338,00 En stock

10CX105YF780E5G

10CX105YF780E5G - Cyclone 10 GX FPGA, 105K LE, 780-BGA | Intel

The Intel 10CX105YF780E5G is a Cyclone 10 GX field-programmable gate array (FPGA) with 105,000 logic elements, 8,641,536 bits of embedded memory, and 284 user I/Os, fabricated on a 20 nm process and housed in a 780-ball flip-chip BGA (FCBGA) package. It belongs to the Cyclone 10 GX family, which targets mid-range applications requiring transceivers, DSP blocks, and low-power operation. The 'E5' speed grade and '0C' (commercial, 0 to 100 C) temperature rating make this part suitable for cost-sensitive, non-automotive designs. The 'F780' suffix indicates the 780-ball FCBGA package, while 'Y' denotes the transceiver-equipped variant with 12.5 Gbps GX transceivers. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks, configurable interconnects, and dedicated hard IP blocks such as transceivers, PLLs, and DSP slices. FPGAs occupy the middle ground between fixed-function ASICs and software-driven microcontrollers: they offer hardware-level parallelism and deterministic latency for applications like video processing, industrial networking, and motor control, while still being reprogrammable in the field. Cyclone 10 GX sits within Intel's low-power FPGA portfolio, optimized for cost and power efficiency while integrating 12.5 Gbps transceivers and a hard memory controller — a feature set historically reserved for higher-end Stratix families. Key features of the 10CX105YF780E5G include 105K logic elements, 38,000 adaptive logic modules (ALMs), 8.439 Mbits of embedded SRAM, 284 user I/Os, hard 12.5 Gbps GX transceivers, variable-precision DSP blocks, and hard PCIe Gen2 controllers. The device supports DDR3 external memory interfaces up to 933 MHz, and integrates a hard floating-point arithmetic block on each DSP. Multiple PLLs and global clock networks provide flexible clock domain management. Cyclone 10 GX uses a 20 nm process with TSMC's low-power technology, enabling a typical core power of less than 1 W per 100K LE plus transceiver contribution. The hard IP for transceivers, PCIe, and memory controllers reduces soft logic overhead, freeing programmable fabric for application-specific logic. The FCBGA-780 package offers controlled-impedance signal routing for high-speed serial links. Typical applications include industrial machine vision, video broadcast and surveillance, software-defined radio, factory automation controllers, and PCIe-based accelerator cards. The combination of transceivers and low power makes Cyclone 10 GX especially attractive for fanless embedded systems with high-speed serial I/O. When designing with this device, allocate PCB stackup budget for the FCBGA's 1.0 mm ball pitch and use Intel's Quartus Prime toolchain for synthesis, place-and-route, and timing closure. Pay close attention to transceiver channel placement and reference clock routing to maintain signal-integrity at 12.5 Gbps. This page synthesizes distributor pricing, package-specific alternatives, and practical Quartus design guidance not consolidated in the official Cyclone 10 GX datasheet.

USD $350,00 En stock

10CX105YF780E6G

10CX105YF780E6G - Cyclone 10 GX FPGA, 104K LE, 780-FCBGA | Altera/Intel

The Altera/Intel 10CX105YF780E6G is a Cyclone 10 GX field-programmable gate array (FPGA) integrating 104,000 logic elements (LE) and 8,641,536 embedded memory bits in a 780-ball flip-chip BGA (FCBGA) package. Part of the Cyclone 10 GX family, this 20 nm device delivers up to 12.5 Gbps transceiver performance, hardware floating-point DSP blocks, and a 1.4 Gbps LVDS SERDES interface, targeting cost-sensitive applications that previously required higher-tier FPGAs. A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit containing programmable logic blocks, configurable interconnect, and hardened I/O and memory resources. FPGAs sit in the broader taxonomy of programmable logic devices -> programmable logic -> logic ICs -> integrated circuits -> semiconductors. The Cyclone 10 GX family uses a 20 nm TSMC fabrication process and embeds dedicated transceiver and PCIe Gen2 hard IP blocks, giving system architects a balanced trade-off between low power, mid-range density, and high-speed serial connectivity compared to ASICs and CPLDs. Key features include 8,641,536 bits (approximately 8.5 Mb) of embedded SRAM, 156 18x19 multipliers (or DSP blocks), up to 284 user I/O pins, six 12.5 Gbps transceivers, and one PCIe Gen2 hard IP block. The device also integrates a hard memory controller, 3.0 Gbps external memory interface, configuration via fast passive parallel (FPP), and active serial (AS) modes. With a 1.0 V core voltage and 0.9 V auxiliary supply, the part is optimized for sub-1.5 W typical power consumption in industrial temperature operation. Architecturally, the Cyclone 10 GX uses a logic-array-block (LAB)-based fabric with adaptive logic modules (ALMs) and a multi-tier routing hierarchy. Hardened transceiver PHY blocks support protocols such as PCIe Gen1/Gen2 x1/x2/x4, 10 GbE (10GBASE-R), and CPRI. The embedded hard memory controllers support DDR3, DDR3L, and LPDDR2 external memory, allowing high-throughput buffering for video, packet processing, and DSP pipelines without consuming fabric resources. Typical applications include industrial machine vision over 10 GbE, wireless backhaul baseband preprocessing, PCIe endpoint cards, broadcast video processing, and low-cost ASIC prototyping. The combination of 12.5 Gbps transceivers, hardened PCIe, and 104K LE makes the 10CX105YF780E6G well-suited for designs where low-end Cyclone V or Spartan-6 parts lack transceivers but full Arria 10 or Kintex-7 devices are over-budget. When designing with this device, ensure signal-integrity simulation for the 12.5 Gbps serial links, and verify PCB stackup meets Intel's transceiver routing guidelines (lossy PCB channel compliance). Power-rail decoupling should follow the Intel Cyclone 10 GX Pin Connection Guidelines for proper POR and configuration sequence. This page synthesizes distributor pricing, drop-in same-package alternatives, comparison data against 10CX085/Cyclone V and Xilinx Artix-7 competitors, and PCB-layout design notes not collected in a single datasheet reference.

USD $580,00 En stock

10CX105YF780I5G

10CX105YF780I5G - Cyclone 10 GX FPGA 105K LE, 8.4Mb | Intel

The Intel 10CX105YF780I5G is a Cyclone 10 GX field-programmable gate array (FPGA) with 105,000 logic elements, 8,641,536 bits of embedded memory, packaged in a 780-ball FCBGA (F780) housing. It delivers 284 user I/O pins with an industrial temperature grade (-40C to +100C) and is targeted at high-throughput, low-power programmable logic applications. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks, interconnect fabric, and I/O cells that the user configures after manufacture. FPGAs occupy the programmable-logic tier of the digital IC hierarchy: ASIC < FPGA < CPLD < microcontroller < standard logic. Within Intel's portfolio, Cyclone 10 GX sits in the low-power, transceiver-rich mid-range, between the smaller Cyclone 10 LP family and the high-end Stratix 10 line. Key features include 38,000 adaptive logic modules (ALMs), integrated transceivers supporting up to 12.5 Gbps, hard memory controllers, and a 0.9 V core supply. The device uses a 20 nm process and supports 1.4 Gbps LVDS, PCIe Gen2 hard IP blocks, and on-chip hardened floating-point multipliers. The 780-ball FCBGA provides the thermal envelope required for full transceiver operation at industrial temperatures. Architecturally, the 10CX105YF780I5G combines a fabric of logic elements, dedicated DSP blocks, M20K memory blocks, and a hardened PCIe Gen2 x4 controller. Transceivers and PLLs are integrated as hard IP to free fabric logic and to deliver deterministic latency for serial protocols, distinguishing the Cyclone 10 GX from soft-logic-only predecessors. Typical applications include industrial machine vision, video bridge and protocol conversion, motor control and drive, broadcast equipment, and PCIe-based data-acquisition cards. The transceiver-rich 780-ball package is well suited to designs that require multi-gigabit serial links alongside programmable logic. When designing with this device, allocate at least one transceiver reference clock and verify PCB routing for 12.5 Gbps signals. The Quartus Prime Lite design suite supports the entire Cyclone 10 GX family, and Intel provides validated reference designs for PCIe Gen2 x4 endpoint applications. This page synthesizes current distributor pricing, drop-in same-package alternatives from the Cyclone 10 GX family, and practical design notes beyond what is found in the manufacturer datasheet, supporting fast sourcing and BOM risk decisions.

USD $115,00 En stock

10CX105YF780I6G

10CX105YF780I6G - Cyclone 10 GX FPGA 104K LE | Intel | 780-FBGA

The Intel 10CX105YF780I6G is a Cyclone 10 GX field-programmable gate array (FPGA) with 104,000 logic elements, 8,641,536 bits of embedded memory, and 284 user I/O pins, housed in a 780-ball Flip-Chip BGA (FCBGA) package. Built on Intel's 20 nm process, this device integrates up to 1.5 Gbps LVDS and 6.144 Gbps transceiver capability, targeting high-bandwidth bridging, video connectivity, and industrial vision applications. The Industrial temperature grade (I) ensures operation from -40C to +100C ambient. An FPGA is a programmable logic device containing configurable logic blocks (CLBs), dedicated DSP blocks, embedded SRAM, and programmable I/O, all interconnected by a programmable routing fabric. FPGAs occupy a middle ground between fixed-function ASICs and general-purpose microcontrollers: they deliver hardware parallelism and deterministic latency for data-pipeline tasks while allowing full logic redesign after PCB fabrication. Within Intel's low-power Cyclone family, the Cyclone 10 GX adds hardened transceivers and an integrated protocol stack for PCI Express Gen2 and 10 GbE (10GBASE-R/KR) on the higher-density members, differentiating it from the transceiver-less Cyclone 10 LP. Key features of the 10CX105YF780I6G include 104K logic elements, 8,641,536 embedded memory bits, 156 embedded 18x18 multipliers, 1 PLL per side, and 6 transceiver channels operating up to 6.144 Gbps. The device also provides 2 hard memory controllers and 1 PCIe Gen2 hard IP block (x4 root port or endpoint). The 780-pin FCBGA package exposes 284 user I/O supporting LVDS, LVCMOS, SSTL, and HSTL I/O standards. Architecturally, the Cyclone 10 GX uses a logic-structural fabric with adaptive logic modules (ALMs) of 8-input fracturable look-up tables, fine-grained DSP blocks with pre-adder and accumulator chains, and embedded M20K memory blocks. Hardened protocol IP reduces soft-logic overhead for PCIe and Ethernet, allowing more design resources to be allocated to application logic. Typical applications include industrial machine vision over GigE Vision or CoaXPress, video broadcast contribution encoders, low-density PCIe endpoint cards, military secure radio, and FPGA-based motor control for industrial drives. Designers choose this part for moderate-density designs that require hardened transceivers without paying the power and cost of higher-end Stratix or Arria 10 devices. When designing with the 10CX105YF780I6G, engineers should plan power-rail sequencing (1.0V core, 2.5V/3.3V aux, 1.8V transceiver PLL), use a minimum of 8 PCB layers with continuous GND planes for transceiver signal integrity, and ensure thermal dissipation through the exposed die on the FCBGA. The Quartus Prime Lite or Pro toolchain is required for synthesis and place-and-route. This page synthesizes distributor pricing, drop-in alternatives from the Cyclone 10 GX family, and practical design notes not found in the manufacturer datasheet alone, helping procurement and engineering teams decide quickly whether 10CX105YF780I6G is the correct fit for their volume production.

USD $1.495,00 En stock

10CX105YU484E5G

10CX105YU484E5G - Cyclone 10 GX FPGA 104K LE 484-UBGA | Intel

The Intel (formerly Altera) 10CX105YU484E5G is a Cyclone 10 GX field-programmable gate array (FPGA) IC with 104,000 logic elements, 8,641,536 bits of embedded memory, and 188 user I/O, housed in a 484-pin U484 Ultra FineLine BGA (UBGA) package. It belongs to the Cyclone 10 GX family, Intel's low-power FPGA line optimized for bandwidth-intensive applications requiring transceivers and DSP throughput. An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit that can be reconfigured by the customer after manufacturing. FPGAs sit in the broader category of programmable logic devices (PLDs), above simple CPLDs in density and capability. The Cyclone 10 GX family specifically targets applications that require high-speed serial transceivers, hardened floating-point DSP blocks, and external memory interfaces, while consuming substantially less power than the Stratix 10 family. Key features include 104K logic elements (LEs), 8,641,536 bits (approximately 8.2 Mbit) of total embedded RAM, 38,000 adaptive logic modules (ALMs) organized into logic array blocks (LABs), and 188 general-purpose I/O. The device integrates 6.144 Gbps transceivers, hard memory controllers, and a hard floating-point DSP subsystem, allowing parallel processing of high-throughput DSP workloads without consuming logic fabric. The 0.9 V core supply enables low static and dynamic power dissipation. The Cyclone 10 GX architecture uses a 20 nm process technology, with logic synthesized into adaptive logic modules (ALMs) each containing an 8-input fracturable look-up table (LUT), two dedicated adders, and four registers. The M20K memory blocks and variable-precision DSP blocks are hardened to deliver deterministic performance and conserve fabric resources for control logic. The hard floating-point DSP subsystem provides IEEE 754 single-precision multiply-accumulate at high block rates. Typical applications include industrial machine vision and video processing, broadcast and professional audio/video equipment, 4K UHD display interfaces, PCIe Gen2 endpoint and root-port designs, and low-cost radar/lidar preprocessing. The 484-UBGA package offers generous I/O density in a compact 19 mm × 19 mm footprint suitable for space-constrained boards. When designing with this device, ensure adequate power-rail decoupling on each of the VCC, VCCPT, VCCA_PLL, and transceiver supply groups, and follow Intel's pin connection guidelines for unused pins. Operating temperature is commercial 0°C to 100°C (TJ); choose the industrial grade variant for extended temperature operation. This page consolidates distributor pricing, drop-in same-family Cyclone 10 GX alternatives, and practical PCB design notes that go beyond the manufacturer datasheet's typical application examples.

USD $275,00 En stock

10CX105YU484E6G

10CX105YU484E6G - 104K LE Cyclone 10 GX FPGA 484-BGA | Intel

The Intel (formerly Altera) 10CX105YU484E6G is a high-density, low-power field-programmable gate array (FPGA) from the Cyclone 10 GX family, fabricated on a 20 nm process. The device integrates 104,000 logic elements, 8,641,536 bits of embedded memory, 188 user I/O pins, and a 12.5 Gbps transceiver subsystem, all housed in a 484-pin Ultra FineLine BGA (UBGA, 19x19 mm) package. It targets high-bandwidth, cost-sensitive applications requiring hardened transceivers, DSP blocks, and PCIe Gen2 hard IP. A field-programmable gate array (FPGA) is a reconfigurable semiconductor integrated circuit whose logic fabric, routing, and I/O can be programmed by the end user after manufacture. FPGAs sit within the programmable-logic device (PLD) hierarchy, which also includes complex programmable logic devices (CPLDs). Architecturally, an FPGA such as the Cyclone 10 GX combines look-up tables (LUTs), flip-flops, block RAM (BRAM), DSP slices, phase-locked loops (PLLs), and increasingly hard intellectual property (IP) cores such as PCIe controllers and multi-gigabit transceivers. This heterogeneity makes FPGAs preferred glue logic, accelerator, and connectivity platforms for embedded, industrial, video, and communications designs. Key differentiating features of the 10CX105YU484E6G include six 12.5 Gbps transceivers, hard PCIe Gen2 x4 IP, up to 480 DSP blocks, 188 single-ended (or 94 differential-pair) general-purpose I/Os, and 3.125 Gbps LVDS support. The device supports LPDDR2, DDR3, and DDR3L external memory interfaces with soft physical layer (PHY) IP, and offers a hardened floating-point arithmetic block set for DSP workloads. Its 20 nm process enables a low static power profile relative to prior 28 nm Cyclone generations. The 10CX105YU484E6G is a fit for high-volume applications such as industrial machine vision with GigE Vision or CoaXPress interfaces, broadcast video processing and encoding, motor control and industrial drive systems, wireless backhaul baseband, and embedded PCIe expansion cards. The integrated 12.5 Gbps transceivers remove the need for external PHY chips on most serial links. Designers targeting low-cost video, HMI, or smart-factory edge nodes benefit from the large logic capacity combined with low-power operation. For designs previously locked to Arria II or earlier, the Cyclone 10 GX delivers substantially higher DSP throughput at comparable static power. When designing in this part, engineers should budget for the device's 1.0 V core VCC supply sequencing and provide robust decoupling per Intel's Power Distribution Network (PDN) guidelines. Pin-out compatible speed-grade and density migrations exist within the Cyclone 10 GX family, allowing pin-compatible movement to lower-cost 10CX085 (85K LE) or higher-cost 10CX220 (220K LE) variants within the same UBGA-484 footprint, depending on yield. JTAG and active serial configuration via the Altera/Intel Quartus Prime toolchain are mandatory. This page synthesizes verified distributor pricing, parametric alternatives within the Cyclone 10 GX family, and practical design notes that complement but do not duplicate the manufacturer datasheet.

USD $65,80 En stock

10CX105YU484I5G

10CX105YU484I5G - 104K-Cell Cyclone 10 GX FPGA | Intel | Industrial Systems

The Intel 10CX105YU484I5G is a Cyclone 10 GX field-programmable gate array (FPGA) with 104,000 logic cells, 8,640,? [DATA_NEEDED: logic elements value] embedded memory bits, and 188 user I/O elements in a 484-pin BGA package. It is designed for configurable digital logic, high-speed interfaces, and industrial applications requiring programmable hardware. The 484-pin package designation is U484, and the ordering code includes the industrial temperature grade and speed-grade identifier I5. An FPGA is a semiconductor device whose digital logic and interconnects are configured after manufacturing. Its hierarchy is FPGA, programmable logic device, configurable logic integrated circuit, and digital semiconductor. Unlike a fixed-function ASIC, an FPGA can implement changing logic functions, interface protocols, control algorithms, and signal-processing datapaths. The Cyclone 10 GX family places programmable logic resources together with I/O and embedded functional blocks, allowing a system designer to consolidate functions that might otherwise require several connected components. The defining feature of 10CX105YU484I5G is its 104,000-cell Cyclone 10 GX architecture. The device provides 188 user I/O resources, 8,640,? [DATA_NEEDED: embedded memory value] memory resources as reported by the distributor description, and 484 package terminals. Its FPGA structure supports configurable parallel logic, serial communication, state machines, timing logic, and custom control blocks. The exact supported transceiver count, maximum operating frequency, power supply limits, and embedded block details must be confirmed from the manufacturer datasheet before final design sign-off. The 10CX105YU484I5G uses a 20 nm process technology, as identified in the distributor listing. This places the component in a high-density programmable-logic class aimed at designs that need more integration than a small CPLD or low-capacity FPGA. The package uses a 484-pin BGA footprint, so PCB escape routing, via-in-pad strategy, solder-mask definition, and signal-integrity analysis are important. The device should be treated as a complex high-speed digital component even where a particular design does not use every available I/O. Typical applications include industrial control and automation, communication equipment, test and measurement, video and image processing, and custom data-acquisition systems. These applications benefit from the ability to revise logic, support multiple interface standards, and adapt timing or protocol behavior without replacing the entire PCB. The 188 I/O resources are especially relevant to systems that aggregate sensors, control signals, memory interfaces, and management buses. When designing with this FPGA, verify all I/O-bank voltage constraints, clocking requirements, configuration architecture, power sequencing, and supported interface standards from the manufacturer documentation. The industrial-grade ordering code should be checked against the complete temperature and qualification wording in the official datasheet. This page combines verified distributor attributes, package and sourcing information, and practical engineering guidance; values not exposed by the supplied search data are explicitly marked rather than estimated.

USD $954,55 En stock

10CX105YU484I6G

10CX105YU484I6G - Cyclone 10 GX FPGA, 104K LE, 484-BGA | Intel

The Intel 10CX105YU484I6G is a Cyclone 10 GX field-programmable gate array (FPGA) delivering 104,000 logic elements, 8,641,536 bits of embedded memory, and 188 user I/O pins in a 484-ball Ultra FineLine BGA (UBGA) package built on a 20 nm process. The device integrates six 12.5 Gbps transceivers, hardware floating-point DSP blocks, and a 72-bit-wide DDR3 SDRAM interface supporting up to 1866 Mbps, targeting cost-sensitive applications that still require multi-gigabit serial connectivity. An FPGA is a programmable logic device whose architecture is built from an array of configurable logic blocks (CLBs), programmable routing, dedicated DSP and block-memory tiles, and high-speed serial transceivers, all wrapped by user I/O. FPGAs sit at the top of the digital-semiconductor hierarchy alongside microcontrollers and ASICs, but are distinguished by hardware-level parallelism and the ability to reconfigure logic after PCB assembly. The Cyclone 10 GX family is Intel's low-power, transceiver-equipped member of the Cyclone 10 series, balancing cost per logic element against bandwidth for video, industrial imaging, and machine-vision pipelines. Key features of the 10CX105YU484I6G include 6 transceivers at up to 12.5 Gbps, 156 DSP blocks (18x18 multipliers), 4 PLLs, 1.4 Gbps LVDS support, and a hard memory controller for external DDR3 up to 1.866 Gbps. The device is available in industrial temperature grade (-40C to 100C) with Pb-free and RoHS-compliant packaging. Typical applications include industrial machine vision, broadcast video processing, ProAV signal routing, motor control and industrial Ethernet bridging, and PCIe Gen2 endpoint designs that need a small-form-factor BGA with high I/O count. The 484-ball UBGA footprint is shared across several Cyclone 10 GX density points and package options, simplifying PCB layout reuse. When designing with this device, ensure that PCB layout meets Intel's transceiver channel guidelines (controlled-impedance routing, AC-coupling capacitors, length matching) and that the Quartus Prime power-estimation flow is run before sign-off to size decoupling capacitors and voltage-rail current. The industrial-grade variant supports extended operation but still requires the same thermal envelope as commercial parts when dissipation exceeds the package's typical theta_JA. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes that are not found in the standalone Intel datasheet, helping engineers shorten the sourcing and qualification cycle for Cyclone 10 GX designs.

USD $372,00 En stock

10CX150YF672E5G

10CX150YF672E5G - Cyclone 10 GX FPGA, 150K LE, 672-FCBGA | Intel

The Intel 10CX150YF672E5G is a Cyclone 10 GX field-programmable gate array (FPGA) integrating 150,000 logic elements, 10,907,648 bits of embedded memory, and 236 general-purpose I/O pins in a 672-ball FineLine BGA (FCBGA) package fabricated on a 20 nm process node. The device belongs to Intel's low-power, transceiver-rich Cyclone 10 GX family and supports up to 6.144 Gbps transceivers, hardware floating-point DSP blocks, and hard memory controllers for mid-range industrial, video, and wireless designs. A field-programmable gate array (FPGA) is a semiconductor device built around a matrix of configurable logic blocks (CLBs), programmable interconnects, and dedicated hardware IP such as DSP slices, block RAM (BRAM), and high-speed serial transceivers. Unlike an application-specific integrated circuit (ASIC), an FPGA's function is defined after manufacture by loading a hardware description language (HDL) bitstream into on-chip SRAM configuration memory. The Cyclone 10 GX family sits within Intel's broader programmable logic hierarchy (FPGA -> programmable logic device -> programmable logic IC -> semiconductor), targeting applications that need higher transceiver bandwidth than Cyclone 10 LP but lower static power and cost than Arria 10 or Stratix 10. Key features of the 10CX150YF672E5G include 150,000 logic elements (LEs), 156 hardware 18x19 multipliers, 490 variable-precision DSP blocks with hardened single-precision floating-point support, 8.5 Mbits of M20K block RAM plus 9.6 Mbits of MLAB memory, six 6.144 Gbps PLLs with fractional-N synthesis, 3.3 V-tolerant LVCMOS/LVDS/LVPECL general-purpose I/O, and a hard PCIe Gen2 x4 controller for embedded compute and storage interfacing. Architecturally the device combines a fine-grained LE fabric with column-based DSP and M20K memory columns, a periphery of high-speed transceivers, and a hardening of common protocol IPs (PCIe, EMIF, JTAG). The 20 nm process enables a die small enough to fit into a 672-ball FCBGA while keeping static power below 1.5 W typical, suiting fanless or limited-cooling enclosures. Typical applications include industrial machine vision and video bridging, factory automation HMI, low-density wireless backhaul modems, broadcast video processing, and PCIe-based accelerator cards. The combination of transceivers, on-chip memory, and DSP makes the part well suited to designs that previously required a discrete ASSP plus an external bridge. When designing in the 10CX150YF672E5G, allocate at least 4 PCB layers for transceiver signal integrity, follow Intel's pin connection guidelines for unused pins and JTAG pull-ups, and use the Quartus Prime Lite/Pro design suite (Cyclone 10 GX device support) for synthesis, place-and-route, and timing closure.

USD $295,00 En stock

10CX150YF672E6G

10CX150YF672E6G - Cyclone 10 GX 150K LE FPGA, 672-FCBGA | Intel

The Intel 10CX150YF672E6G is a Cyclone 10 GX field-programmable gate array (FPGA) offering 150,000 logic elements, 10,907,648 embedded memory bits, and 236 (18x18) multipliers in a 672-ball FCBGA package. It targets mid-range, power-sensitive applications that need transceiver-rich I/O and DSP bandwidth at industrial-grade operating conditions. The part ships as an Enhanced speed-grade (-E6G) device rated for industrial temperature operation. A Field-Programmable Gate Array (FPGA) is a reconfigurable integrated circuit that combines programmable logic blocks, routing interconnect, and hardened IP blocks such as transceivers, DSP blocks, and memory controllers. FPGAs occupy a unique position in the semiconductor hierarchy: more flexible than an application-specific standard product (ASSP) yet more deterministic and parallel than a microprocessor. The Cyclone 10 GX family specifically sits at the intersection of low static power, integrated 12.5 Gbps transceivers, and hardened PCI Express Gen2 controllers - making it a mainstream workhorse for video, industrial, and wireline bridge designs. Key features of the 10CX150YF672E6G include up to 12.5 Gbps multi-protocol transceivers, hard PCI Express Gen2 x4 IP blocks, hardened variable-precision DSP blocks supporting 18x18 multipliers and 27-bit pre-adder, and up to 10.9 Mbits of embedded SRAM distributed between M20K block memory and LUTRAM. The device is fabricated on Intel's 20 nm process, balancing leakage versus performance for thermally constrained enclosures. Per-bank programmable I/O banks support LVDS, LVCMOS, and memory interfaces up to DDR3. Architecturally, the Cyclone 10 GX uses an Adaptive Logic Module (ALM) as its basic building block - each ALM contains an 8-input fracturable look-up table, two dedicated adders, and four registers. Combined with the Core fabric, Memory, and DSP blocks, the 10CX150 delivers approximately 150K logic elements with deterministic routing and timing closure supported by the Quartus Prime design suite. Typical applications include industrial machine vision over CoaXPress or GigE Vision, broadcast video processing with 12G-SDI and DisplayPort bridging, low-cost 10G Ethernet aggregation switches, motor control and digital drive systems, and PCI Express Gen2 endpoint cards. The transceiver and hard PCIe IP blocks also suit radar/LiDAR front-end preprocessing and software-defined radio baseband. When designing with this part, pay attention to the FCBGA 672-ball pitch and PCB stack-up. Use Intel's Cyclone 10 GX pin connection guidelines to assign unused I/O, enable internal weak pull-ups where required, and follow the High Speed Board Design Guidelines for the 12.5 Gbps transceiver channels. Plan a complete Quartus Prime-based power tree early - the device uses multiple supply rails (VCC, VCCPT, VCCR_GXB, VCCT_GXB) that must be sequenced. This page synthesizes distributor pricing, drop-in package alternatives within the Cyclone 10 GX and Cyclone 10 LP families, and practical design notes not found in the manufacturer datasheet alone.

USD $124,90 En stock

10CX150YF672I5G

10CX150YF672I5G - Cyclone 10 GX FPGA, 150K LE, 672-FCBGA | Intel

The Intel (formerly Altera) 10CX150YF672I5G is a Cyclone 10 GX field-programmable gate array (FPGA) integrating 150,000 logic elements, 10,907,648 bits of embedded memory, and 236 user I/O pins in a 672-ball flip-chip BGA (FCBGA) package. It belongs to the low-power, transceiver-rich Cyclone 10 GX family fabricated on a 20 nm process, delivering transceiver rates up to 12.5 Gbps for cost-sensitive high-volume applications. The device operates over the industrial -40C to +100C temperature range with a 0.9 V core supply. An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that combines programmable logic blocks, configurable interconnects, and dedicated DSP/memory blocks into a single silicon die. Within the broader taxonomy, an FPGA sits as a specialized subclass of programmable logic devices (PLDs) and, more generally, as an application-specific integrated circuit (ASIC) alternative under the digital semiconductor hierarchy: FPGA -> programmable logic -> logic IC -> integrated circuit. Cyclone 10 GX specifically targets cost-optimized, transceiver-enabled designs that previously required more expensive mid-range FPGAs. Key features of the 10CX150YF672I5G include up to 12.5 Gbps multi-gigabit transceivers, a hard memory controller for DDR3/DDR4/LPDDR3 external memory, PCI Express Gen2 hard IP blocks, and a 1.4 Gbps LVDS serializer/deserializer interface. The 672-FCBGA package supports high I/O count with dedicated high-speed transceiver and LVDS pairs. With 54,770 adaptive logic modules (ALMs) and 156 18x19 multipliers, the device balances logic density with DSP throughput for video bridging, machine vision, and industrial wireless backhaul. Architecturally, the Cyclone 10 GX family uses a 20 nm process with hard IP blocks for transceivers, PCIe Gen2, and external memory controllers, freeing programmable fabric for application logic. The hard transceiver PHY eliminates the soft-SERDES power penalty and reduces latency for protocols such as 10 GbE, CPRI, and JESD204B. According to Intel Cyclone 10 GX device documentation, the 150 K LE variant targets designs that need richer transceiver count and DSP than Cyclone V but do not require the higher logic capacity of Arria 10. Typical applications include industrial machine vision frame grabbers, video broadcast equipment, PCIe Gen2 endpoint cards, 5G small-cell fronthaul, low-latency financial trading, and automotive ADAS sensor aggregation. The transceiver bandwidth and PCI Express Gen2 hard IP make it well suited for line-rate 10G Ethernet switching and CPRI 4.9G wireless backhaul. The industrial temperature range supports factory floor deployment without thermal screening. When designing with this FPGA, allocate sufficient PCB area for the 672-ball FCBGA (27 mm x 27 mm, 1.0 mm ball pitch) and follow Intel's recommended PCB stack-up for impedance-controlled transceiver channels. Decoupling requirements, transceiver channel routing, and JTAG/AS configuration pin placement should follow the manufacturer pin connection guidelines. This page synthesizes distributor pricing, drop-in alternative guidance, and practical design notes not found in the manufacturer datasheet alone.

USD $278,40 En stock

10CX150YF672I6G

10CX150YF672I6G - Cyclone 10 GX FPGA, 150K LE, 672-BGA | Intel

The Intel 10CX150YF672I6G is a Cyclone 10 GX Field Programmable Gate Array (FPGA) delivering 150,000 logic elements, 54,770 logic array blocks, 10,907,648 bits of embedded memory, and 236 user I/Os in a 672-ball FCBGA package. Built on a low-power 20 nm process, the Cyclone 10 GX family targets cost- and power-sensitive applications that still require transceivers and hard memory controllers, with up to 6.144 Gbps transceivers supporting PCIe Gen2 x4 and external memory interfaces up to DDR3-1866. What is a Cyclone 10 GX FPGA? FPGAs are programmable logic devices containing configurable logic blocks, routing, memory blocks, DSP blocks, and hardened IP that can be rewired at silicon level after fabrication. Cyclone 10 GX sits in Intel's (formerly Altera's) low-cost, low-power product line as a bridge between the Cyclone V family and the higher-end Arria 10, inheriting transceiver and hard memory controller IP from Arria while retaining the low static and dynamic power profile expected of Cyclone-class parts. Key features include 150K logic elements (LEs), 54,770 adaptive logic modules (ALMs), 6.6 Mb of embedded SRAM organized as M20K blocks, variable-precision DSP blocks supporting 18x18 and 27x27 multiplication, 4.6 Mb of general-purpose memory, and up to 6.144 Gbps multi-gigabit transceivers. The device integrates a hard PCIe Gen2 x4 IP block, hard memory controllers for DDR3 with ECC, and a quad-core ARM Cortex-A9 hard processor subsystem is NOT included (that is Cyclone V SoC); this part is FPGA-only with Cortex-class soft cores optional. The 672-ball FCBGA uses a 27x27 mm substrate with 1.0 mm ball pitch, providing generous signal and power pin allocation for high-speed serial links. Industrial temperature grade (-40C to +100C Tj) supports deployment in factory automation, outdoor wireless backhaul, and ruggedized video processing. Power is supplied through dedicated VCC, VCCA, and VCCR pins separated between core, PLL, transceiver, and I/O banks, enabling clean power sequencing and isolation. Typical applications include industrial machine vision with GigE Vision or CoaXPress interfaces, video broadcast and ProAV processing with 3G-SDI/HD-SDI bridging, low-cost PCIe add-in cards, factory automation and motor control, and 4K/8K video wall driving. The combination of hardened transceivers, hard PCIe, and low power also suits IoT gateways that need deterministic Ethernet or cellular fronthaul. Design consideration: the 1.0 mm BGA pitch demands careful PCB stack-up planning. A minimum 8-layer stack with continuous GND planes adjacent to high-speed signals is recommended to maintain signal integrity on 6 Gbps serial links. Power ramp sequencing for VCC_CORE must precede VCCA_PLL to avoid latch-up, and reference clock jitter must remain below 100 fs RMS for jitter-compliant PCIe Gen2 link training.

USD $215,00 En stock

10CX150YF780E5G

10CX150YF780E5G - Cyclone 10 GX FPGA 150K LE | Intel | 780-FBGA

The Intel 10CX150YF780E5G is a Cyclone 10 GX field-programmable gate array (FPGA) integrating 150,000 logic elements, 10,907,648 bits of embedded memory, and 284 user I/Os in a 780-ball flip-chip BGA (FCBGA) package. As a member of the Cyclone 10 GX family, it targets mid-range, transceiver-rich applications such as video bridging, industrial machine vision, and high-speed serial interfacing. The "E5G" speed grade and -5 commercial temperature rating make it a cost-optimized choice for volume production designs. An FPGA (field-programmable gate array) is a semiconductor device built around an array of configurable logic blocks (CLBs) interconnected by a programmable routing fabric. Within the broader hierarchy, an FPGA belongs to programmable logic devices (PLDs), which in turn sit within the digital semiconductor category alongside ASICs, microcontrollers, and DSPs. The Cyclone 10 GX family specifically adds hardened transceivers, PCI Express Gen2 hard IP blocks, and a variable-precision DSP block set optimized for arithmetic throughput. Key features of the 10CX150YF780E5G include up to 12.5 Gbps transceivers, hardened PCI Express Gen2 x4 support, variable-precision DSP blocks, and on-chip memory up to approximately 10.9 Mbits. The device supports common memory interfaces including DDR3, DDR3L, LPDDR3, and QDRII+/RLDRAM3 through dedicated PHY blocks, simplifying external memory integration without soft logic overhead. The Cyclone 10 GX architecture uses a 20 nm process technology and Intel's adaptive logic module (ALM) building block. Each ALM contains eight inputs with a fracturable lookup table and two dedicated registers, allowing efficient mapping of arithmetic, multiplexer, and register-heavy functions. The transceiver tiles are positioned along the die edges to optimize signal integrity for high-speed serial links. Typical applications include industrial machine vision, broadcast video processing, video surveillance infrastructure, PCI Express add-in cards, and protocol bridging between legacy video standards and DisplayPort or HDMI interfaces. The transceiver count makes the device well suited for any application requiring multi-lane serial I/O. When designing with this device, pay close attention to PCB layout: the FCBGA package demands microvia stack-ups, matched-length traces for transceiver lanes, and continuous ground reference planes under high-speed signals. The Intel Quartus Prime design suite handles synthesis, place-and-route, and timing closure for this part. This page combines verified distributor pricing, drop-in alternative cross-references, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for component evaluation and procurement decisions.

USD $160,00 En stock

10CX150YF780E6G

10CX150YF780E6G - Cyclone 10 GX FPGA 150K LE, 780-FCBGA | Intel

The Intel 10CX150YF780E6G is a Cyclone 10 GX field-programmable gate array (FPGA) from the 20nm process family, integrating 150,000 logic elements (LEs), approximately 10.9 Mbits of embedded memory, and 284 user I/O pins in a 780-ball flip-chip BGA (FCBGA) package with industrial -40C to +100C operating range. A Field-Programmable Gate Array (FPGA) is a semiconductor device built around a matrix of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as transceivers, DSP blocks, and memory controllers. FPGAs sit within the broader taxonomy of programmable logic devices (PLD) and bridge the gap between fixed-function ASICs and software-driven processors, offering hardware-level parallelism with reconfigurable logic. Cyclone 10 GX specifically targets high-volume, cost-sensitive applications that require transceiver connectivity, hardened memory controllers, and moderate DSP throughput. The 10CX150YF780E6G delivers key features including up to 12.5 Gbps GX transceivers, hardware PCI Express Gen2 hard IP blocks, variable-precision DSP blocks for fixed- and floating-point arithmetic, and support for external memory interfaces including DDR3, DDR4, LPDDR3, and QDR II+ with dedicated hard PHY. The device integrates 1.6 GHz ARM Cortex-A9-class hard processor system support through soft IP and offers on-chip voltage regulation for core and I/O rails. Architecturally, the Cyclone 10 GX uses a 20nm TSMC process with adaptive logic modules (ALMs) and a multi-tier routing fabric. Each ALM contains eight fracturable look-up tables (LUTs) and dedicated adders, while MLAB memory blocks can be configured as either dual-port RAM or shift registers. Transceiver channels support protocols such as PCIe Gen2 x4, 10GbE KR, CPRI, and JESD204B without external PHY silicon. Typical applications include industrial machine vision cameras, broadcast video processing, low-density wireless backhaul, factory automation controllers, and cost-optimized PCIe acceleration cards. The combination of transceivers and DSP makes the 10CX150YF780E6G especially suited to video bridging, protocol bridging, and sensor aggregation designs. When designing with this part, allocate sufficient PCB area for FCBGA breakout and route high-speed transceiver channels with controlled impedance. Use Intel Quartus Prime software for synthesis and place-and-route, and validate timing closure before tape-out. The -E6G speed grade targets the fastest commercial timing, so thermal management must keep junction temperature within Intel-recommended limits. This page synthesizes Intel Cyclone 10 GX datasheet parameters, distributor pricing as of 2026-09-05, drop-in alternative FPGAs from the same Intel family, and practical design notes not found in the standalone datasheet PDF.

USD $575,00 En stock

10CX150YF780I5G

10CX150YF780I5G - 150K LE Cyclone 10 GX FPGA 780-FBGA | Intel

The Intel (Altera) 10CX150YF780I5G is a Cyclone 10 GX Field Programmable Gate Array (FPGA) featuring 150,000 logic elements, 10,907,648 memory bits, and 284 user I/Os, packaged in a 780-ball FineLine BGA (FBGA). Built on TSMC's 20nm process, it delivers high-bandwidth transceiver and DSP capability at low static and dynamic power, targeting cost- and power-sensitive applications that still require 10G transceiver connectivity. An FPGA (Field Programmable Gate Array) is a reconfigurable semiconductor device whose logic fabric, embedded memory blocks, DSP blocks, and I/O transceivers are defined by a user-programmed configuration bitstream after manufacture. Within Intel's portfolio the Cyclone family sits below Stratix in cost and power, and the GX sub-family adds multi-gigabit transceivers that enable protocols such as PCIe Gen2, 10GbE, CPRI, and JESD204B without external PHY chips. The 10CX150YF780I5G is therefore commonly used as a bridge between high-speed serial links and parallel digital processing in mid-volume designs. Key features include 150K logic elements, 484 18x18 multipliers (or 242 27x27 multipliers) for DSP, 6.6 Mbit of embedded M20K memory, twelve 10.3125 Gbps transceivers, and hard PCIe Gen2 IP blocks. The F780 package exposes 284 general-purpose I/Os supporting LVDS, LVCMOS, SSTL, and HSTL standards with 1.0/1.2/1.5/1.8/2.5/3.0 V support. An industrial temperature grade (I5G, -40C to +100C ambient) makes the part suitable for harsh-environment deployments including factory floor, outdoor wireless, and aerospace subsystems. Typical applications include industrial machine vision, broadcast video processing, wireless backhaul fronthaul, test and measurement, software-defined radio, and PCIe card prototyping. Designers select this device when they need Stratix-class transceivers but in a Cyclone power and price envelope. When designing in the 10CX150YF780I5G, pay close attention to transceiver reference-clock jitter, decoupling strategy for the 0.9V core and 1.8V/3.3V auxiliary rails, and PCB stackup for the FBGA escape. Quartus Prime software is required for synthesis, place-and-route, and bitstream generation; licenses are available in the Intel FPGA Self-Service Licensing Center.

USD $165,00 En stock

10CX150YF780I6G

10CX150YF780I6G - 150K LE Cyclone 10 GX FPGA 780-FBGA | Intel

The Intel (Altera) 10CX150YF780I6G is a Cyclone 10 GX field-programmable gate array (FPGA) built on a 20 nm low-power process, delivering 150,000 logic elements (LE), approximately 10.9 Mbits of embedded memory (M20K), and 484 18x19 multipliers in a 780-ball FineLine BGA (FBGA) package. The device integrates up to 12 transceivers at 3.125 Gbps (GX variant) and supports high-speed serial interfaces for cost-sensitive video, industrial, and machine-vision applications. A Field-Programmable Gate Array (FPGA) is a programmable semiconductor device that allows designers to configure custom digital logic, memory blocks, DSP slices, and I/O after fabrication. FPGAs sit in the broader taxonomy of programmable logic devices (PLDs) -> complex programmable logic devices (CPLDs) -> FPGAs -> high-performance FPGAs, and are widely used for parallel data processing, hardware acceleration, and interface bridging where ASIC NRE cost is unjustified. The Cyclone 10 GX family targets cost-sensitive mid-density designs that still need transceiver bandwidth and DSP throughput. Key features include 1.25 GHz LVDS performance on the FPGA fabric, hard memory controllers for DDR3/DDR3L/LPDDR3 external memory, hard PCIe Gen2 hard IP blocks, and hardened floating-point multipliers. The device supports up to 480 user I/O pins (industrial grade, 6-speed grade, 780-pin FBGA, the F780 package code) and integrates a hardened Security feature set for bitstream protection. Industrial temperature range is -40C to +100C (junction), with the I6G speed grade denoting the industrial tier. The Cyclone 10 GX architecture combines a logic fabric of adaptive logic modules (ALMs), M20K SRAM blocks, and variable-precision DSP blocks. The 20 nm process allows higher integration at lower static power versus the prior 28 nm Cyclone V generation, while embedded hard IP (PCIe Gen2, transceivers, memory controllers) frees up fabric resources for user logic. Typical applications include industrial machine-vision cameras, video broadcast and professional AV equipment, motor control and industrial Ethernet interfaces, low-cost PCIe Gen2 endpoint cards, and 4K video processing. Transceivers enable 3G-SDI, DisplayPort, and GigE Vision connectivity. Design considerations: power estimation must use the Intel Early Power Estimator (EPE) before pin assignment; an FPGA of this density typically requires a multi-layer PCB with continuous GND planes and decoupling per Intel's Cyclone 10 GX pin connection guidelines. This page synthesizes distributor pricing, parametric alternatives in the same FBGA-780 footprint, and practical design notes not found in the manufacturer datasheet.

USD $325,00 En stock

10CX150YU484E5G

10CX150YU484E5G - 150K LE Cyclone 10 GX FPGA | Intel | BGA-484

The Intel (formerly Altera) 10CX150YU484E5G is a Cyclone 10 GX field-programmable gate array (FPGA) with 150,000 logic elements, 54,770 adaptive logic modules (ALMs), and 10.652 Mbit of embedded memory, housed in a 484-pin U484 BGA package with 188 user I/Os. It belongs to the low-power, high-throughput Cyclone 10 GX family fabricated on a 20 nm process, delivering transceivers, hard memory controllers, and variable-precision DSP blocks for cost-sensitive mid-range designs. What is an FPGA? A Field-Programmable Gate Array is a reprogrammable semiconductor device whose logic fabric, routing, and I/O can be configured by the designer after manufacture. Within Intel's portfolio the Cyclone 10 GX sits below the high-end Stratix 10 line and above the Cyclone V / Cyclone 10 LP families, targeting applications that need integrated transceivers, moderate logic density, and 1.0 Gb/s-to-12.5 Gb/s serial links without the power envelope of a Stratix-class device. It is also a power-management IC sibling category: FPGAs are configured and powered by companion voltage regulators and supervisors such as the TPS7A4701 or LTM4644. Key features of the 10CX150YU484E5G include 150K logic elements, 54,770 ALMs, 10.652 Mbit embedded RAM, 188 single-ended or 94 differential-pair user I/Os, and integrated 12.5 Gbps transceivers. The -E5 speed grade and 0.9 V core supply support industrial-temperature environments, while the U484 package (19 mm × 19 mm, 1.0 mm ball pitch) keeps PCB complexity and BOM cost manageable. The 10CX150YU484E5G uses a hard-logic fabric with M20K SRAM blocks, variable-precision DSP slices, and PCIe Gen2 hard IP, all bonded through an Altera/Intel multi-gigabit transceiver (PMA + PCS) layer. Engineers target it for video bridging, machine-vision preprocessing, industrial control planes, and small-form-factor software-defined radio front ends where deterministic latency and tight power budgets coexist. Typical applications include industrial machine vision (Basler/Arena interfaces), broadcast video processing (SMPTE 2022 / 2110 bridging), PCIe Gen2 endpoint cards, and low-density 10G Ethernet aggregation. The 484-ball package is well-suited to mid-complexity PCIe cards, FMC carrier designs, and SmartNIC reference platforms. When designing with the 10CX150YU484E5G, pay attention to transceiver reference-clock jitter, M20K memory bandwidth, and decoupling for the 0.9 V core rail. Intel recommends a 6-layer PCB with continuous power planes and a Quartus Prime power analyzer run before sign-off. This page synthesizes distributor pricing, drop-in Cyclone 10 GX equivalents, and Quartus Prime design-flow notes not found in the standalone manufacturer datasheet.

USD $128,65 En stock

10CX150YU484E6G

10CX150YU484E6G - Cyclone 10 GX 150K LE FPGA, 484-BGA | Intel

The Intel 10CX150YU484E6G is a Cyclone 10 GX field-programmable gate array (FPGA) from Intel's Cyclone 10 GX family, delivering 150,000 logic elements (LE) and 10,907,648 bits of embedded memory (10.4 Mbits) on a 20nm process technology node, housed in a 484-ball Ultra BGA (UBGA) package with industrial-grade temperature grading. The Cyclone 10 GX family targets high-bandwidth, low-power FPGA applications requiring hardened transceivers and a balanced mix of logic, memory, and DSP resources at a low-cost programmable-logic price point. A field-programmable gate array (FPGA) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnects, embedded memory, DSP slices, and increasingly hardened protocol IP such as transceivers and PCIe interfaces. FPGAs sit at the top of the programmable-logic hierarchy: SRAM-based programmable fabric -> programmable logic device (PLD) -> FPGA -> programmable SoC (when paired with hard CPU cores), enabling hardware-level parallelism for compute, signal processing, and high-speed serial I/O. Compared with an ASIC, an FPGA offers in-system reprogrammability and faster time-to-market at higher unit cost. Key features include high-bandwidth transceivers, a hard memory controller subsystem, variable-precision DSP blocks, and a hardened PCIe Gen2 hard IP block. The 484-ball UBGA package provides a compact, surface-mount footprint with controlled-impedance routing access to the transceiver banks. The device supports configuration via external flash, JTAG, or in-system update, allowing remote bitstream loading in deployed systems. The 20nm process node balances static and dynamic power, making this device suitable for thermally constrained industrial environments. From an architecture perspective, the Cyclone 10 GX uses an SRAM-based configuration memory backed by an internal configuration controller. The transceiver tiles are positioned on dedicated banks, while the FPGA fabric is laid out as a fabric of LABs (logic array blocks), M20K embedded memory blocks, and variable-precision DSP blocks. The 484-ball package gives access to a defined subset of user I/O banks and full access to the transceiver/PLL pins. Typical applications include industrial machine vision, video surveillance and broadcast video processing, industrial Ethernet switching and protocol bridging, motor control and industrial drive interfaces, low-cost 10G/6G optical transport, and PCI Express endpoint cards for embedded compute. The combination of transceivers and DSP resources makes this device a strong fit for any application requiring real-time signal processing with moderate logic density. When designing with this device, use Intel Quartus Prime (Standard or Pro edition, depending on variant support) for synthesis, place-and-route, and bitstream generation, and observe the transceiver reference-clock jitter budget and decoupling-capacitor placement guidance in the Cyclone 10 GX device datasheet for signal-integrity-compliant board layouts. This page synthesizes distributor pricing, package-pinout detail, drop-in same-package alternatives from the Cyclone 10 GX family, and practical board-design notes not found in the manufacturer datasheet alone.

USD $124,55 En stock

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