10AS032E3F29I2LG vs 10AS032E4F27I3LG Comparación
Comparación detallada lado a lado de 10AS032E3F29I2LG por Intel y 10AS032E4F27I3LG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 10AS032E3F29I2LG | 10AS032E4F27I3LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.390,00 | $1.085,10 |
| Device Family | Arria 10 SX SoC FPGA | — |
| Logic Elements (LE) | 320,000 | — |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Process Technology | 20 nm | 20 nm |
| Core Voltage | 0.9 V | — |
| Hard Processor Core Frequency | 1.5 GHz | — |
| Encapsulado | 780-pin FCBGA (29x29 mm) | 672-pin FCBGA (F27, 27x27 mm) |
| Package Code | F29 (FBGA, FC) | — |
| Transceiver Data Rate | Up to 17.4 Gbps | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| DSP Blocks | Yes (variable-precision, floating-point) | Hardened floating-point DSP (family-level) |
| Memory Interfaces | DDR4, DDR3, QDRIV SRAM | DDR3 / DDR4 with hard controllers (family-level) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Estado RoHS | Compliant | Compliant |
| Pitch | [DATA_NEEDED: ball pitch] | — |
| Total I/O Pins | [DATA_NEEDED: I/O count] | — |
| Family | — | Arria 10 SX SoC FPGA |
| Logic Elements | — | 320,000 |
| Hard Processor Subsystem (HPS) | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Clock Frequency | — | 1.5 GHz |
| Speed Grade | — | E4 (-4, mid-tier) |
| Temperature Grade | — | Industrial (-40C to +100C) |
| Lead-Free | — | Yes |
| Nivel MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| Transceivers | — | Up to 24 channels, up to 14.1 Gbps (family-level) |
| Configuration Method | — | JTAG, ASx4, FPP (family-level) |