10AS066H2F34I1HG vs 10AS066H3F34E2LG Comparación
Comparación detallada lado a lado de 10AS066H2F34I1HG por Intel y 10AS066H3F34E2LG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 10AS066H2F34I1HG | 10AS066H3F34E2LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3.500,00 | $2.875,00 |
| Series | Arria 10 SX | — |
| Logic Elements | 660,000 | 660,000 |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 1.5 GHz | — |
| Process Technology | 20 nm | 20 nm |
| User I/O Count | 492 | — |
| Encapsulado | 1152-pin FC-FBGA (35x35 mm) | 1152-ball FCBGA (F34), 35 mm x 35 mm |
| Tensión de alimentación | 0.9 V | — |
| Rango de temperatura de funcionamiento | -40C to +100C (Industrial) | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | Compliant | Compliant |
| Configuration Method | SRAM-based, JTAG | — |
| On-chip Memory | Embedded memory blocks (M20K) | — |
| DSP Blocks | Variable-precision DSP | — |
| Transceivers | Multi-gigabit transceivers (up to 12.5 Gbps) | Up to 24 multi-gigabit transceivers (family-level) |
| Hard Memory Controller | Yes (DDR3/DDR4/LPDDR3) | — |
| PCIe Hard IP | PCIe Gen2/Gen3 | — |
| Family | — | Arria 10 SX |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Core Voltage | — | 0.9 V |
| Maximum Core Frequency | — | 1.5 GHz |
| Memory Controllers | — | Hard DDR3/DDR4 PHY (per Arria 10 SoC datasheet) |
| Operating Temperature Grade | — | Industrial (per F34 ordering code) |
| Device Type | — | System-on-Chip FPGA (SoC) |
| Lead-Free | — | Yes |
| Configuration Image Support | — | Dual configuration, partial reconfiguration (family-level) |