10AS066H3F34I2LG vs 10AS066H3F34E2LG Comparación
Comparación detallada lado a lado de 10AS066H3F34I2LG por Altera y 10AS066H3F34E2LG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 10AS066H3F34I2LG | 10AS066H3F34E2LG |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $2.875,00 |
| Product Type | System-on-chip FPGA | — |
| FPGA Family | Arria 10 SX | — |
| Logic Elements | 660000 | 660,000 |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Stated Frequency | 1.5 GHz | — |
| I/O Count | 492 I/O | — |
| Technology | 20 nm | — |
| Core Voltage Snippet | 0.9 V | — |
| Cell Count | 660000 cells | — |
| Package Pin Count | 1152 pins | — |
| Package Type | FCBGA | — |
| Package Dimensions | 35 mm x 35 mm | — |
| Terminal Form | Ball | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Temperature Grade | Industrial | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Arria 10 SX |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Process Technology | — | 20 nm |
| Core Voltage | — | 0.9 V |
| Maximum Core Frequency | — | 1.5 GHz |
| Encapsulado | — | 1152-ball FCBGA (F34), 35 mm x 35 mm |
| Memory Controllers | — | Hard DDR3/DDR4 PHY (per Arria 10 SoC datasheet) |
| Transceivers | — | Up to 24 multi-gigabit transceivers (family-level) |
| Operating Temperature Grade | — | Industrial (per F34 ordering code) |
| Device Type | — | System-on-Chip FPGA (SoC) |
| Lead-Free | — | Yes |
| Configuration Image Support | — | Dual configuration, partial reconfiguration (family-level) |