10AX115N4F40E3LG vs 10AX115R2F40E1SG Comparación
Comparación detallada lado a lado de 10AX115N4F40E3LG por Intel y 10AX115R2F40E1SG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 10AX115N4F40E3LG | 10AX115R2F40E1SG |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6.200,00 | $6.875,00 |
| Product Type | FPGA - Field Programmable Gate Array | — |
| Family | Arria 10 GX | Arria 10 |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 | — |
| Embedded Memory Bits | 68,857,856 (approx. 53 Mb) | — |
| M20K Memory Blocks | 2,738 | — |
| MLAB Memory (Kb) | 12,962 | — |
| DSP Blocks | 600 (variable-precision) | 1,518 (variable-precision 20x19) |
| 18x19 Multipliers | 1,536 | — |
| Maximum User I/O | 624 | — |
| Transceivers | 24 (up to 14.1 Gbps) | GX transceivers up to 14.2 Gbps |
| Transceiver Data Rate | 1.0 to 14.1 Gbps | — |
| PCIe Hard IP | Up to Gen3 x8 | — |
| Process Technology | TSMC 20 nm | 20 nm TSMC tri-gate (FinFET) |
| Core Voltage | 0.85 V / 0.9 V typical | — |
| Encapsulado | 1517-BBGA, FCBGA (40 x 40 mm) | 1517-ball FCBGA (F40) 40x40 mm |
| Temperatura de funcionamiento | -40C to +100C (extended) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant | Compliant |
| Configuration Method | Serial / JTAG / Active Serial (AS) | — |
| Lead-Free | Yes | — |
| Series | — | Arria 10 GX |
| Embedded Memory (bits) | — | 68,857,856 |
| Number of I/O | — | 342 |
| Hard Memory Controllers | — | Yes (DDR4, DDR3, LPDDR3, QDR IV) |
| Hard PCIe Block | — | PCIe Gen3 x8 |
| Speed Grade | — | -2 |
| Temperature Grade | — | Extended (-E1) |
| Lead Free | — | Yes |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Configuration | — | SRAM-based, supports partial reconfiguration |