10AX115R4F40I3SG vs 10AX115N4F40I3SG Comparación
Comparación detallada lado a lado de 10AX115R4F40I3SG por Altera y 10AX115N4F40I3SG por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
10AX115R4F40I3SG - Arria 10 GX FPGA, 1.15M LEs, 1517-FCBGA | Altera
10AX115R4F40I3SG ✓ ActivoComparación de especificaciones
| Parámetro | 10AX115R4F40I3SG | 10AX115N4F40I3SG |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8.470,00 | $3.500,00 |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements | 1,150,000 | — |
| Embedded Memory | 68,857,600 bits | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| User I/O | 342 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Core Voltage | 0.9 V | — |
| Process Technology | 20 nm | — |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| Encapsulado | 1517-BBGA, FCBGA (F40) | 1517-BBGA, FCBGA (F40), 40 x 40 mm, 1.00 mm pitch |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Lead-Free / RoHS | Yes / Compliant | — |
| Nivel MSL | 3 | 3 (per JEDEC J-STD-020) |
| Configuration Memory | SRAM-based, volatile | — |
| DSP Blocks | Hardened variable-precision DSP | [DATA_NEEDED: DSP block count] |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count] |
| Embedded Memory Bits | — | 68,857,856 |
| Maximum User I/O | — | 600 |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Process Node | — | 20 nm |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCC core voltage] |
| Configuration | — | Serial, Parallel, and Avalon-ST supported |
| Estado RoHS | — | Compliant |
| Hardened IP | — | PCIe Gen3, 100G Ethernet MAC (per Quartus IP library) |
| Device Family Position | — | Mid-range 20 nm transceiver FPGA |