10CL055YF484I7G vs 10CL040YU484I7G Comparación
Comparación detallada lado a lado de 10CL055YF484I7G por Intel y 10CL040YU484I7G por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 10CL055YF484I7G | 10CL040YU484I7G |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $46,09 | $48,75 |
| Series | Cyclone 10 LP | — |
| Family | Cyclone® 10 LP | Cyclone 10 LP |
| Logic Elements (LE) | 55,856 | 39,600 |
| Embedded Memory (bits) | 2,396,160 | — |
| Number of Logic Array Blocks (LAB) | 3,478 | — |
| Number of M9K Memory Blocks | 260 | — |
| Embedded Multipliers (18x18) | 156 | — |
| Maximum User I/Os | 321 | — |
| Number of PLLs | 4 | — |
| Global Clock Networks | 20 | — |
| Temperatura de funcionamiento | -40C to +100C (Industrial) | -40 C to +100 C (Industrial) |
| Speed Grade | I7 | — |
| Encapsulado | 484-BGA (FBGA, FineLine BGA) | 484-pin UBGA (Ultra FineLine BGA) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Method | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Core Voltage | 1.2 V | 1.0 V to 1.2 V |
| Auxiliary Voltage | 2.5 V / 3.3 V | — |
| Estado RoHS | Compliant | Compliant |
| Process Technology | 60 nm low-power CMOS | TSMC 60 nm low-power |
| Hard Memory Controller | DDR2 / DDR3 / LPDDR2 | — |
| Configurable Logic Blocks (CLB) | — | 2,475 |
| Embedded Memory | — | 1,161,216 bits (M9K blocks) |
| Embedded 18x18 Multipliers | — | 66 |
| Maximum User I/O | — | 325 |
| General-Purpose PLLs | — | 4 |
| Ball Pitch | — | 0.8 mm |
| Configuration Mode | — | JTAG / AS / PS |
| Supply Form | — | Tray |