5CSEBA2U23A7N vs 5CSEBA2U19C7N Comparación
Comparación detallada lado a lado de 5CSEBA2U23A7N por Intel y 5CSEBA2U19C7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
5CSEBA2U19C7N - Cyclone V SE SoC FPGA, 25K LE, Dual ARM Cortex-A9 | Intel
5CSEBA2U19C7N ✓ ActivoComparación de especificaciones
| Parámetro | 5CSEBA2U23A7N | 5CSEBA2U19C7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $99,50 | $16,90 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| MPN Code | 5CSEBA2U23A7N (Cyclone V SE A2, U23 package) | — |
| Logic Elements | 25,000 LE | 25,000 LE |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 700 MHz | — |
| Process Technology | 28 nm low-power | TSMC 28 nm low-power |
| User I/O | 188 | — |
| Encapsulado | 672-UBGA (23x23 mm) | 484-pin UBGA (19x19 mm, 1.0 mm pitch) |
| Speed Grade | 7 | C7 |
| Temperature Grade | A (Commercial, 0C to +85C) [DATA_NEEDED: exact junction range] | — |
| Estado RoHS | Compliant (per ampheo listing) | Compliant |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Operating Voltage (Core) | 1.1 V (typical FPGA core, multi-rail HPS) | — |
| Configuration Scheme | HPS-boot of FPGA fabric via configuration QSPI | — |
| Embedded Memory | M10K blocks (count [DATA_NEEDED: exact M10K/M20K count]) | 1,400 Kbits (M9K + MLAB) |
| DSP Blocks | Variable-precision DSP (count [DATA_NEEDED: exact count]) | 66 (variable-precision 18x18) |
| PLLs | Fractional PLLs (count [DATA_NEEDED: exact PLL count]) | — |
| Adaptive Logic Modules (ALMs) | — | 9,430 ALM |
| ALUTs | — | 9,430 |
| HPS Processor | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | — | 925 MHz |
| L1 Cache (per core) | — | 32 KB I-cache + 32 KB D-cache |
| L2 Cache | — | 512 KB shared |
| User I/O Pins | — | [DATA_NEEDED: exact user I/O count] |
| Temperatura de funcionamiento | — | Commercial / Industrial (TJ from data) |