5CSXFC6C6U23C8NES vs 5CSXFC6C6U23I7LN Comparación
Comparación detallada lado a lado de 5CSXFC6C6U23C8NES por Intel y 5CSXFC6C6U23I7LN por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 5CSXFC6C6U23C8NES | 5CSXFC6C6U23I7LN |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $119,55 |
| Family | Cyclone V SX | Cyclone V SX SoC FPGA |
| Device Type | SoC FPGA (FPGA + ARM Cortex-A9 HPS) | — |
| Logic Elements | 110,000 | 110K |
| Hard Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Clock Frequency (max) | 600 MHz | — |
| Process Node | 28 nm TSMC low-power | — |
| Embedded Memory (M10K + MLAB) | 5,140 Kbits (approx) | — |
| DSP Blocks (18x19 multipliers) | 112 | — |
| User I/O Pins | 224 | — |
| Encapsulado | 672-pin UBGА (23x23 mm) | 672-UBGA (23x23 mm) |
| Speed Grade | 8 (commercial) | — |
| Temperatura de unión de funcionamiento | 0C to +85C (commercial) | — |
| External Memory Interfaces | DDR2, DDR3, LPDDR2 | — |
| Hard PCIe Gen2 Controllers | 2 | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Estado RoHS | Compliant | Compliant |
| Device Variant | — | 5CSXFC6C6U23 |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum HPS Clock Frequency | — | 925 MHz |
| Temperatura de funcionamiento | — | -40C to +100C (Industrial) |
| Process Technology | — | 28 nm low-power |
| Embedded Memory | — | [DATA_NEEDED: total Kbits] |
| DSP Blocks | — | Variable-precision, supports 18x18 and 27x27 multipliers |
| Transceivers | — | Integrated high-speed transceivers |
| HPS Peripherals | — | USB, GbE, SD/SDIO/MMC, UART, SPI, I2C |
| Memory Interfaces | — | DDR3, DDR2, LPDDR2 |
| I/O Standards | — | LVDS, LVCMOS, SSTL |
| Configuration | — | HPS boot from NAND/NOR/SD/eMMC; FPGA via Quartus Prime |