5CSXFC6D6F31A7N vs 5CSXFC5D6F31I7N Comparación
Comparación detallada lado a lado de 5CSXFC6D6F31A7N por Intel y 5CSXFC5D6F31I7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 5CSXFC6D6F31A7N | 5CSXFC5D6F31I7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $345,50 | $138,20 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX SoC FPGA |
| Logic Elements | 110,000 | 85,000 |
| Process Technology | 28 nm TSMC low-power | 28 nm low-power |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 700 MHz | — |
| Core Voltage | 1.1 V | 1.1 V |
| User I/O Count | 288 | — |
| Encapsulado | 896-ball FBGA (31 x 31 mm) | 896-ball FBGA (31 x 31 mm) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Automotive / AEC-Q100 | — |
| Automotive Qualification | AEC-Q100 | — |
| Embedded Memory | Approximately 5.5 Mbits (M10K + MLAB) | — |
| DSP Blocks | Up to 224 (18 x 18 multipliers) | 18 x 18 multipliers |
| Hard Memory Controller | DDR2 / DDR3 / LPDDR2 / QDR II+ | — |
| Hard IP Peripherals | PCIe Gen2, GbE, USB 2.0 OTG, NAND, SD/MMC | — |
| Configuration | FPGA + HPS subsystem, integrated | — |
| Estado RoHS | Compliant | Compliant |
| Nivel de sensibilidad a la humedad (MSL) | [DATA_NEEDED: MSL level] | — |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz |
| Package Pitch | — | 1.0 mm |
| Temperatura de funcionamiento | — | -40 C to +100 C (Industrial, TJ) |
| Memory Interfaces | — | DDR2, DDR3, LPDDR2 |
| I/O Standards | — | LVDS, LVTTL, LVCMOS, RSDS |
| Transceivers | — | Present (Cyclone V SX transceiver variants) |
| Nivel MSL | — | 3 (per JEDEC J-STD-020, typical for BGA) |