74HC165D,652 vs 74HC165D Comparación
Comparación detallada lado a lado de 74HC165D,652 por Nexperia y 74HC165D por Nexperia. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Nexperia
74HC165D,652 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,652 ✓ ActivoComparación de especificaciones
| Parámetro | 74HC165D,652 | 74HC165D |
|---|---|---|
| Marca | Nexperia | Nexperia |
| Categoría | Logic ICs | Logic ICs |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,16 | $0,15 |
| Logic Type | Shift Register | Shift Register (Parallel-in / Serial-out, PISO) |
| Función | Parallel or Serial to Serial | 8-bit parallel-load / serial-in shift register with complementary serial outputs |
| Number of Elements | 1 | 1 |
| Number of Bits per Element | 8 | — |
| Tipo de salida | Differential (complementary Q7 and Q7-bar) | Complementary CMOS (Q7, Q7-bar) |
| Supply Voltage (VCC) | 2 V to 6 V | — |
| Logic Family | 74HC (high-speed Si-gate CMOS) | 74HC / 74HCT (high-speed Si-gate CMOS, LSTTL pin-compatible) |
| Input Type | CMOS (HC); pin-compatible with TTL/LSTTL | Standard CMOS (HC); TTL-compatible variant is 74HCT165 |
| Temperatura de funcionamiento | -40 °C to +125 °C | -40 C to +125 C |
| Encapsulado | 16-SOIC (SOT109-1), 0.154" (3.90 mm) width | 16-pin SOIC (SOT109-1) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Número de pines | 16 | — |
| Standard Compliance | JEDEC standard no. 7A | — |
| Pin Compatible With | Low-power Schottky TTL (LSTTL) | — |
| Parallel Load | Asynchronous via SH/LD-bar | Asynchronous, active-low SH/LD |
| Serial Data Input | DS (for daisy-chaining) | — |
| Clock Input | CP (rising-edge triggered) with clock inhibit (CE-bar) | — |
| Estado RoHS | Compliant | Compliant |
| Bits per Element | — | 8 |
| Supply Voltage (Vcc) | — | 2.0 V to 6.0 V |
| Serial Input | — | Synchronous DS on rising CLK edge |
| Nivel MSL | — | 1 (unlimited) |
| JEDEC Compliance | — | JEDEC standard no. 7A |