74HC165D vs 74HC165D,652 Comparación
Comparación detallada lado a lado de 74HC165D por Nexperia y 74HC165D,652 por Nexperia. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Nexperia
74HC165D,652 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,652 ✓ ActivoComparación de especificaciones
| Parámetro | 74HC165D | 74HC165D,652 |
|---|---|---|
| Marca | Nexperia | Nexperia |
| Categoría | Logic ICs | Logic ICs |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,15 | $0,16 |
| Logic Type | Shift Register (Parallel-in / Serial-out, PISO) | Shift Register |
| Number of Elements | 1 | 1 |
| Bits per Element | 8 | — |
| Función | 8-bit parallel-load / serial-in shift register with complementary serial outputs | Parallel or Serial to Serial |
| Supply Voltage (Vcc) | 2.0 V to 6.0 V | — |
| Input Type | Standard CMOS (HC); TTL-compatible variant is 74HCT165 | CMOS (HC); pin-compatible with TTL/LSTTL |
| Tipo de salida | Complementary CMOS (Q7, Q7-bar) | Differential (complementary Q7 and Q7-bar) |
| Logic Family | 74HC / 74HCT (high-speed Si-gate CMOS, LSTTL pin-compatible) | 74HC (high-speed Si-gate CMOS) |
| Parallel Load | Asynchronous, active-low SH/LD | Asynchronous via SH/LD-bar |
| Serial Input | Synchronous DS on rising CLK edge | — |
| Temperatura de funcionamiento | -40 C to +125 C | -40 °C to +125 °C |
| Encapsulado | 16-pin SOIC (SOT109-1) | 16-SOIC (SOT109-1), 0.154" (3.90 mm) width |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 1 (unlimited) | — |
| Estado RoHS | Compliant | Compliant |
| JEDEC Compliance | JEDEC standard no. 7A | — |
| Number of Bits per Element | — | 8 |
| Supply Voltage (VCC) | — | 2 V to 6 V |
| Número de pines | — | 16 |
| Standard Compliance | — | JEDEC standard no. 7A |
| Pin Compatible With | — | Low-power Schottky TTL (LSTTL) |
| Serial Data Input | — | DS (for daisy-chaining) |
| Clock Input | — | CP (rising-edge triggered) with clock inhibit (CE-bar) |