9DBV0441AKILF vs SI53112-A00AGM Comparación
Comparación detallada lado a lado de 9DBV0441AKILF por Renesas Electronics y SI53112-A00AGM por Skyworks Solutions. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Renesas Electronics
9DBV0441AKILF - 1.8V PCIe Gen1-3 4-Ch Clock Buffer | Renesas
9DBV0441AKILF ✓ ActivoSkyworks Solutions
SI53112-A00AGM - 12-Output PCIe Gen 3 ZDB Buffer | Skyworks
SI53112-A00AGM ✓ ActivoComparación de especificaciones
| Parámetro | 9DBV0441AKILF | SI53112-A00AGM |
|---|---|---|
| Marca | Renesas Electronics | Skyworks Solutions |
| Categoría | Clock & Timing | Clock & Timing |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $2,75 | $3,76 |
| Device Type | Clock Buffer / Zero-Delay Buffer (ZDB) / Fanout Buffer | — |
| Función | PCIe Gen1-2-3 and 125 MHz Ethernet clock distribution | — |
| Número de salidas | 4 | 12 differential pairs (24 outputs) |
| Tipo de salida | HCSL (PCIe Gen1-2-3 compliant) with integrated 100 ohm terminations | HCSL (current-mode differential) |
| Input Type | HCSL-compatible differential (common clock) | — |
| Output Frequency (PCIe mode) | 100 MHz | — |
| Output Frequency (Ethernet mode) | 125 MHz (software selectable) | — |
| Supply Voltage (VDD) | 1.8 V | — |
| PLL | Internal, pin/software selectable bandwidth and PLL bypass | — |
| Programmable Slew Rate | Yes, per output | — |
| Programmable Output Amplitude | Yes, per output | — |
| Integrated Output Termination | Zo = 100 ohm | — |
| Encapsulado | 32-VFQFPN Exposed Pad, 5x5 mm | 64-pin QFN (9x9 mm) with exposed pad |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| RoHS | Compliant (Lead-Free) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Product Type | — | 1:12 Zero-Delay Buffer (ZDB) |
| Compliance Specification | — | Intel DB1200ZL |
| Input Frequency Range | — | 25 MHz to 200 MHz |
| Output Frequency Range | — | 100 MHz / 133.33 MHz (hardware pin selectable) |
| Additive Phase Jitter | — | < 0.5 ps RMS (12 kHz to 20 MHz) |
| Input-to-Output Delay | — | < 50 ps (ZDB PLL alignment) |
| Core Supply Voltage | — | 3.3 V |
| Estado RoHS | — | Compliant |
| Supported Protocols | — | PCIe Gen 1/2/3/4, Intel QPI, SAS, SATA, SMI |