ADS62P48IRGC25 vs ADC34J44IRGZ25 Comparación
Comparación detallada lado a lado de ADS62P48IRGC25 por Texas Instruments y ADC34J44IRGZ25 por Texas Instruments. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Texas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ ActivoTexas Instruments
ADC34J44IRGZ25 - Quad 14-bit 125 MSPS ADC w/ JESD204B | Texas Instruments
ADC34J44IRGZ25 ✓ ActivoComparación de especificaciones
| Parámetro | ADS62P48IRGC25 | ADC34J44IRGZ25 |
|---|---|---|
| Marca | Texas Instruments | Texas Instruments |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,20 | $107,04 |
| Resolución | 14 bit | 14 bit |
| Number of Channels | 2 (Dual) | 4 |
| Sample Rate (max) | 210 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential analog inputs | Differential |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) | — |
| Analog Supply Voltage | 1.8 V | — |
| Digital Supply Voltage | 3.3 V | — |
| Rango de temperatura de funcionamiento | -40 C to +85 C (Industrial) | -40C to +85C (Industrial) |
| Encapsulado / Carcasa | 64-VQFN (RGC) 9x9 mm (HVQCCN) | — |
| Recuento de pines | 64 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 3 | — |
| Estado RoHS | Compliant | Compliant |
| Lead Free | Yes | — |
| Input Clock Type | LVDS differential clock | — |
| Internal Dither | Yes (programmable) | Yes |
| Programmable Gain | Yes (improves SFDR at lower FS inputs) | — |
| Sample Rate | — | 125 MSPS |
| Full-Scale Input Range | — | 1.0 Vpp |
| SNR (f_IN = 70 MHz) | — | 72 dBFS |
| SFDR (f_IN = 70 MHz) | — | 86 dBc |
| Channel-to-Channel Isolation | — | 105 dB |
| Power Consumption (per channel, 160 MSPS) | — | 203 mW |
| Digital Interface | — | JESD204B (Subclass 0/1/2) |
| Number of JESD204B Lanes | — | 1 per ADC (up to 160 MSPS) |
| Tensión de alimentación | — | 1.8 V (single supply) |
| Multi-Chip Synchronization | — | Yes (SYSREF/SYNC~) |
| Encapsulado | — | 48-VQFN (7x7 mm, RGZ) |