ATMEGA64A-MUR vs ATMEGA64L-8MUR Comparación
Comparación detallada lado a lado de ATMEGA64A-MUR por Microchip Technology y ATMEGA64L-8MUR por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microchip Technology
ATMEGA64A-MUR - AVR 8-bit MCU 64KB Flash 16MHz QFN-64 | Microchip
ATMEGA64A-MUR ✓ ActivoComparación de especificaciones
| Parámetro | ATMEGA64A-MUR | ATMEGA64L-8MUR |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,42 | $5,16 |
| Core Architecture | AVR 8-bit RISC | — |
| Program Memory Size | 64KB (32K x 16) Flash | 64 KB (32K x 16) FLASH |
| Program Memory Type | ISP Flash, read-while-write | In-System Programmable FLASH |
| EEPROM Size | 2KB | 2 KB |
| SRAM Size | 4KB (4K x 8) | — |
| Maximum Clock Speed | 16 MHz | — |
| Supply Voltage Range | 2.7 V to 5.5 V | 2.7 V to 5.5 V (L version) |
| Number of I/O | 53 | 53 |
| General Purpose Working Registers | 32 | — |
| Instruction Set | 130 powerful instructions, most single-cycle | — |
| Timers/Counters | 4 flexible timer/counters plus real-time counter | — |
| Oscillator Type | Internal | External (XTAL) |
| Encapsulado / Carcasa | 64-VFQFN Exposed Pad (9x9 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperature Grade | Industrial (-40C to +85C) | — |
| Packaging | Tape & Reel | — |
| Programming Interface | ISP (In-System Programmable), JTAG | — |
| Core Processor | — | AVR |
| Core Size | — | 8-Bit |
| Speed | — | 8 MHz |
| RAM Size | — | 4 KB SRAM |
| Temperatura de funcionamiento | — | -40C to +85C |
| Encapsulado | — | 64-QFN (9x9 mm) MLF |
| Peripherals | — | Brown-out Detect/Reset, POR, PWM, WDT |
| Connectivity | — | I2C (TWI), SPI, UART/USART x2 |
| Data Converters | — | 8-channel 10-bit ADC |
| Timers | — | Two 8-bit, Two 16-bit |
| JTAG | — | Yes (on-chip debug and boundary scan) |
| Architecture | — | Advanced RISC, 130 instructions, 32 x 8 registers |