CDK2308DILP64 vs CDK2308AILP64 Comparación
Comparación detallada lado a lado de CDK2308DILP64 por MaxLinear y CDK2308AILP64 por MaxLinear. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | CDK2308DILP64 | CDK2308AILP64 |
|---|---|---|
| Marca | MaxLinear | MaxLinear |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $7,20 |
| Resolución | 10 bit | 10 bit |
| Number of Channels | 2 (Dual) | 2 (Dual) |
| Sampling Rate (max) | 80 MSPS | — |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS (programmable) | — |
| Architecture | Pipelined ADC | Pipelined |
| Input Type | Single-ended analog | Differential / Single-ended analog |
| Power Dissipation | 78 mW per channel at 80 MSPS | [DATA_NEEDED: power in mW] |
| Supply Voltage (AVDD) | [DATA_NEEDED: AVDD nominal voltage] | — |
| Supply Voltage (DRVDD) | [DATA_NEEDED: DRVDD nominal voltage] | — |
| Input Bandwidth | [DATA_NEEDED: -3 dB input bandwidth] | [DATA_NEEDED: input bandwidth MHz] |
| SNR | [DATA_NEEDED: SNR at full scale] | [DATA_NEEDED: SNR dBFS] |
| SFDR | [DATA_NEEDED: SFDR] | — |
| ENOB | [DATA_NEEDED: effective number of bits] | — |
| Encapsulado | 64-QFN (9x9 mm) | 64-pin QFN (LP) 9x9 mm with exposed pad |
| Rango de temperatura de funcionamiento | -40 C to +85 C | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | Compliant | Compliant (per distributor listings) |
| Power-Down Modes | Per-channel standby, chip standby, full power-down | — |
| Track-and-Hold Amplifier | Integrated, optimized for IF frequencies | — |
| Manufacturer | — | Exar (MaxLinear) |
| Part Number | — | CDK2308AILP64 |
| Sampling Rate (Grade ILP64) | — | 20 MSPS |
| Family Maximum Sampling Rate | — | 80 MSPS (per family datasheet) |
| Analog Supply Voltage | — | +3.3 V |
| Digital Supply Voltage | — | +3.3 V |
| Data Interface | — | Parallel CMOS / TTL |
| Internal Reference | — | Yes (bandgap) |
| INL (Integral Non-Linearity) | — | [DATA_NEEDED: INL in LSB] |
| DNL (Differential Non-Linearity) | — | [DATA_NEEDED: DNL in LSB] |